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NFS 표준을 위한 개선된 프로브를 이용한 칩 수준 NFP 측정값 교정 및 검증
이필수(Pil-soo Lee),위재경(Jae-Kyung Wee),김부균(Boo-Gyoun Kim),최재훈(Jai-Hoon Choi),여순일(Soon-il Yeo) 대한전자공학회 2012 電子工學會論文誌-SD (Semiconductor and devices) Vol.49 No.6
본 논문에서는 near-field scanning (NFS) 시스템을 위한 새로운 보정 방법을 제시하였다. 제안된 교정 방법은 새로운 near-field probe (NFP)와 circular patch patterns (CPPs) and meander patterns (MPs) 같은 새로 고안된 패턴으로 구성되어 있다. 제안된 패턴들은 IEC61967-2과 6에 언급된 기존의 방법과 비교해 공간 해상도을 개선하고 NFP의 교정 절차를 단순화하기 위해 사용하였다. 또한 감쇄 특성에 대한 NFP의 길이 효과를 8mm와 30mm의 길이를 가지고 조사하였다. 이러한 특성을 위해 지름 (D)가 20, 40, 60, 그리고 100mm의 CPP를 만들었고 여러 가지 폭과 간격을 가지는 MP를 설계하고 제작하였다. 단순화된 교정 절차를 이용하여 공간 해상도와 측정 높이 사이의 역 관계를 발견하였다. 테스팅 결과는 측정 높이 200 μm에서 120 μm의 공간해상도를 복잡한 수정 알고리듬 없이 8GHz 아래에서 얻을 수 있음을 보였다. 제작 단가를 위해 모든 패턴과 NFP는 일반적인 고가의 LTCC 대신 저가의 PCB (FR-4)을 이용해 실현하였다. 이결과를 칩 수주 EMC 사용 가능성을 검증하기 Sub-micron scale 동작이 가능한 NFSS을 제작하였고, 제안된 NFP를 이용하여 사용 칩의 측정결과 200㎛ 패턴의 형태를 정확하게 묘사가 가능한 수준의 해상도를 확보하여 칩 수준 EMC 검증에 사용 할 수 있음을 증명하였다. New calibration method for the near-field scanning (NFS) system is presented. The proposed calibration method consisted of a new near-field antenna (NFP) and newly devised patterns as circular patch patterns (CPPs) and meander patterns (MPs). The proposed patterns were used for improving spatial resolutions and simplifying a calibration procedure of the NFP compared to the conventional method defined in the IEC61967-3 and 6. Also, the effect of the length of NFPs on attenuation characteristics was investigated with length of 8mm and 30mm. For them, we designed and fabricated CPPs of diameter (D) = 20, 40, 60, and 100mm and MPs of various widths and spaces. We found the reverse relations between spatial resolutions and heights of measuring points by using simplified calibration procedure. The testing result shows that the spatial resolution of 120 μm at height of 200 μm was verified without complex correlation algorithms under 8GHz. For manufacturing cost all patterns and the NFP were realized with low-cost fabrication using PCB (FR-4) not by a conventional LTCC process. For verification of chip-level EMC from the results, near-field scanning system (NFSS) having step resolution of Sub-micron scale was produced and by using the proposed NFSS and proposed NFP measurement of chip shows accurately the shape of the resolution of 200 ㎛ patterns for securing a high level of chip-level EMC verification.
EMI 저감을 위해 분할된 전원/접지 평판 구조에서의 방사성 방출 분석
이장훈(Jang-hoon Lee),이필수(Pil-soo Lee),이태헌(Tae-Heon Lee),김창균(Changgyun Kim),송인채(Inchae Song),위재경(Jae-Kyung Wee) 大韓電子工學會 2010 電子工學會論文誌-SD (Semiconductor and devices) Vol.47 No.6
본 논문에서는 시스템 모듈에서 발생하는 EMI를 줄이기 위해 분할된 전원/접지 평판 구조에 의해 발생하는 방사성 방출 (Radiated emission)을 분석하였다. 분석을 위해 다양한 조건을 갖는 시험 기판(Test board)에 대한 자기장과 전기장을 시뮬레이션하고 측정하여 비교하였다. 이 분석 결과는 입력 신호의 주파수 대역에서 반사계수의 위상이 0˚에 근접하도록 하며, 입력 신호의 주파수와 분할된 전원/접지 평판 구조의 공진주파수가 일치하지 않도록 분할된 접지 갭의 폭과 위치를 결정함으로써 방사성 방출을 줄일 수 있음을 보여준다. 또한, 스티칭 커패시터(Stitching capacitor)를 사용하여 방사성 방출을 저감시킬 수 있으며, 방사성 방출을 효과적으로 저감시키기 위해 입력 신호의 주파수에서 반사계수의 크기를 낮추고 위상이 0˚에 근접하도 록 스티칭 커패시터의 값과 위치를 결정할 필요가 있음을 알 수 있다. In this paper, we analyzed radiated emission generated by the split power/ground plane structures in order to reduce EMI in system modules. The magnetic fields and electric fields were simulated and measured on the test boards under various conditions. In order to reduce radiated emission, we have to determine spacing and location of the split ground gap so that input signal frequency does not coincide with the resonance frequency of the split power/ground plane structure and the phase of reflection coefficient is close to 0° at input signal frequency. Moreover, we found that inserting a stitching capacitor could reduce the radiated emission. Low magnitude of reflection coefficient and the phase close to 0° are required to reduce radiated emission. It is necessary to properly decide value and location of a stitching capacitor to fulfil those requirements.
게잡이 원숭이에 있어 rHuEPO(HM10760)의 단회 투여 후 혈액학 및 혈액생화학적 변화
김충용(Choong-Yong Kim),이현숙(Hyun-Sook Lee),이필수(Pil-Soo Lee),하창수(Chang-Su Ha),권세창(Se-Chang Kwon),이관순(Gwan Sun Lee),송창우(Chang-Woo Song),한상섭(Sang-Seop Han) 한국독성학회 2006 Toxicological Research Vol.22 No.1
Changes in hematology and serum biochemistry after treatment of recombinant human erythropoietin (rHuEPO, HM10760) were screened in 4 male cynomolgus monkeys (Macaca fascicularis). Four monkeys, composed of a treatment group of HM10760 and a positive control group of Aranesp<SUP>®</SUP>, were subcutaneously administered at same dose of 100 ㎍/㎏. Both groups did not show any change in body weights and food consumption for 4 weeks compared with those of pretreatment. Both groups did not show any change in total leukocyte count (WBC) and platelet count, while both groups showed increased platelet distribution width (PDW) percentage in HM10760 group during a period from day 5 to day 59 and in Aranesp<SUP>®</SUP> group during a period from day 9 to day 26. Both groups showed increases in red blood cells (RBC), hemoglobin (HGB), and hematocrit (HCT) approximately 10 days after treatment compared with those of pretreatment (day 0). The increased levels of RBC, HGB, and HCT were much higher in HM10760 than in Aranesp<SUP>®</SUP> by the increases of 3.2%~ 12.5% for RBC, 3.8%~17.1% for HCT, and 1.85%~11% for HGB. Both groups showed increases in red cells distribution width (RDW) and reticulocyte (RET) compared with those of pretreatment, showing the highest peak from day 9. The increased level of RET lasted up to day 14 in Aranesp<SUP>®</SUP> group, while it lasted up to day 23 in HM10760 group. The increased level of RDW lasted up to day 59, it was much higher in HM10760 by the increase of 10.1%~17.6% than in Aranesp<SUP>®</SUP> group. In serum biochemistry, both groups showed a decrease in chloride level compared with those of pretreatment. These findings indicated that HM10760 increased RBC, HGB, HCT, RDW, and RET compared with those of pretreatment, and the increased levels were much higher in HM10760 than in Aranesp<SUP>®</SUP>.
개 코로나바이러스 불활화 백신에 대한 개와 기니픽 간의 면역반응 비교
안동준,김병한,정병열,이철현,전우진,이필수,정갑수,An, Dong-jun,Kim, Byoung-han,Jung, Byeong-yeal,Yi, Chul-hyun,Jeon, Woo-jin,Lee, Pil-soo,Chung, Gab-soo 대한수의학회 2005 大韓獸醫學會誌 Vol.45 No.2
Canine coronavirus (CCV) causes a mild gastroenteritis in dogs. The virus is highly contagious. Although the virus was isolated more than thirty years ago, canine coronavirus infection continues to be a widespread problem. Mixed infections with both CCV and canine parvovirus (CPV) are common. Four kinds of commercial killed CCV vaccines are available in Korea. All the commercial vaccines should pass the National Assay for Veterinary Biologicals prior to release. For the potency test of CCV vaccine, it is necessary to use CCV antibody free dogs. The test requires not only kennels but high cost. To develop easy, efficient and economic potency test method for killed CCV vaccine using laboratory animals, a series of experiments with rabbits and guinea pigs were carried out in this study. In the preliminary test, the guinea pigs showed better immune responses than rabbits. The guinea pig was also easy to manage. So guinea pig was selected for the potency test animals. When the guinea pigs were inoculated twice with one dose of vaccine intramuscuarly each, slower and a little lower SN antibody titers were induced in guinea pigs than in dogs (about 2 kg body weight Beagle strain) given the same posology as guinea pigs'. It was concluded that guinea pigs could be substituted for dogs in the potency test of killed CCV vaccine.
입력 위상 잡음 억제 및 체배 주파수의 듀티 사이클 보정을 위한 VCO/VCDL 혼용 기반의 다중위상 동기회로
하종찬(Jong-Chan Ha),위재경(Jae-Kyung Wee),이필수(Pil-Soo Lee),정원영(Won-Young Jung),송인채(In-Chae Song) 大韓電子工學會 2010 電子工學會論文誌-SD (Semiconductor and devices) Vol.47 No.11
본 논문은 입력 클록의 고주파 위상 잡음 억제와 정확한 듀티 사이클을 갖는 체배 주파수 생성을 위하여 Voltage-Controlled Oscillator(VCO)/Voltage-Controlled Delay Line(VCDL) 혼용기반의 다중 위상 Delay-Locked Loop(DLL)를 제시한다. 이 제안된 구조에서, 다중 위상 DLL은 혼용 VCO/VCDL의 입력 단에 nMOS 소스 결합 회로 기반의 이중 입력 차동 버퍼를 사용한다. 이것은 고주파 입력 위상 잡음 억제를 위하여 전 대역 통과 필터 특성을 갖는 기존 DLL의 입/출력 위상 전달을 저주파 통과 필터 특성을 갖는 PLL의 입/출력 위상 전달로 쉽게 변환시킬 수 있다. 또한, 제안된 DLL은 추가적인 보정 제어 루프 없이 단지 듀티 사이클 보정 회로와 위상 추적 루프를 이용하여 체배 주파수의 듀티 사이클 에러를 보정할 수 있다. 0.18㎛ CMOS 공정을 이용한 시뮬레이션 결과에서, 제안된 DLL의 출력 위상 잡음은 800㎒의 입력 위상 잡음을 갖는 1㎓ 입력 클록에 대하여 -13㏈ 이하로 개선된다. 또한, 40%∼60%의 듀티 사이클 에러를 갖는 1㎓ 동작 주파수에서, 체배 주파수의 듀티 사이클 에러는 2㎓ 체배 주파수에서 50±1%이하로 보정된다. This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with 0.18㎛ CMOS technology, the output phase noise of the proposed DLL is improved under -13㏈ for 1㎓ input clock with 800㎒ input phase noise. Also, at 1㎓ operating frequency with 40%∼60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under 50±1% at 2㎓ the input clock.