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이민섭(Minseop Lee),정철균(Cheolgyun Jung),김대겸(Daegyoum Kim) 대한기계학회 2021 대한기계학회 춘추학술대회 Vol.2021 No.11
Thin structures with elasticity found in nature are under the influence of gravity in the process of interacting with uniform flow. In addition, a situation in which an elastic sheet collides with another rigid body may occur in the course of motion. In this study, the stability and post-critical behaviors of a flag, which interacts with uniform flow under gravity and is in contact with a nearby rigid wall, are experimentally investigated to elucidate the effects of gravity and contact on flutter dynamics. By varying the free-stream velocity and the distance between the clamped leading edge of the flag and the rigid wall, different modes are classified. The distance between the clamped leading edge of the flag and the rigid wall is a critical parameter. Therefore, we introduce a new dimensionless velocity considering this parameter and confirm that the transition of the mode is determined by this new dimensionless velocity.
3-3.5㎓ 대역폭 지원을 위한 오류 보상 듀티 주기 검출기를 구현한 듀티 주기 교정기
이민섭(MinSeop Lee),박현수(HyunSu Park),심진철(JinCheol Sim),권영욱,전진우(JinWoo Jeon),유정식(Jeongsik Yoo),박수호(SooHo Park),김철우(ChulWoo Kim) 대한전자공학회 2020 대한전자공학회 학술대회 Vol.2020 No.8
High-speed memory interface system such as double data rate(DDR) memories require an exact 50% duty cycle system clock for optimal valid data window. This paper presents a duty cycle corrector (DCC) using error compensate duty cycle detector(DCD). The proposed DCC consists of a DCD which implemented error detecting and correcting function, a duty-cycle adjuster, controller and output buffer. The proposed DCC circuit has been implemented and fabricated in a 28-nm CMOS process and occupies 2742<SUP>2</SUP>. The acceptable input clock frequency is from 3㎓ to 3.5㎓ and acceptable duty cycle variation is ±20%. The measured maximum duty-cycle error for the 50% duty-rate is 3.8%.