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최흥문,문상재 경북대학교 전자기술연구소 1980 電子技術硏究誌 Vol.1 No.1
This paper proposed microprocessor-based design of an automatic test pattern generator, which can generate complete fault detection test sets for the combinational logic networks, provided with only the logic equations of the networks under test. Once the logic equations for the networks under test are transformed into NAND-NAND equations using GDT(generalized DeMorgans theorem), the networks can be transformed into the easily testable NAND-NAND test equivalent networks. Applying the transformed equations to the generator through only 3 input keys, the test sets can be automatically generated. Upon applying these test sets to the networks under test, this generator also detects and locates the faults and saves the resulted test information.
Classification of Document Image Blocks Based on Textural Features and BP
최흥문,심재창,Joong Soo Kim,Jeong Hwan Lee 대한전자공학회 1994 ISPACS:Intelligent Signal Processing and Communica Vol.1 No.1
This paper introduces an efficient document block classification method based on statistical textural features and using BP(backpropagation) algorithm. The image is first processed by Sobel operator and then segmentation is done by smearing the block. Seven features are extracted from SGLDM(spatial grey level dependence matrix) which is the textural features of grey level document image. Block classification is accomplished using a neural network of BP algorithm. This method classifies the image block into nine types in detail. The experiments show excellent results of very few errors and the fine classification of document blocks.
Concurrent Edge Detection and Prominent Edge Enhancement Using a Cooperative Neural Network
최흥문,전준형 대한전자공학회 1994 ISPACS:Intelligent Signal Processing and Communica Vol.1 No.1
In this paper, we proposed an efficient algorithm in which edge detection, prominent edge enhancement and binarization, and orientation detection can be done concurrently by using cooperative neural network. We applied 4 cooperative neural masks to each pixel, and we also give a threshold bound in the neural network to find out the prominent edge accurately. In contrast to the conventional edge detection algorithm, the proposed algorithm does not, require the postprocessing such as thresholding for the binarization or feature extraction for image recognition. The experiments are conducted on various complex 251 X 256 images, which have small grey level differences in 256-grey level, and the results show that prominent edge enhancement and binarization , and orientation detection can be done concurrently without postprocessing. And the proposed algorithm have good characteristics for the important feature detection and noise rernoval, and the results of the experiment show that it is efficient for neural network based target recognition system under study which highly requires those characteristics.
최흥문,고광식,김진호 경북대학교 전자기술연구소 1989 電子技術硏究誌 Vol.10 No.1
This paper proposed a design and implementation method of multimicrocomputer network with reconfigurable interconnection network for real time parallel processing. With the temporal and the spatial parallelism from parallel processing algorithm. we modeled the system into a real time parallel pipeline. We designed a multimicrocomputer network under a real time constraints and implemented a test bed with a crossbar network to measure the simulation parameter. Simulation results show that using the proposed desigh method, we can easily implement a multimicrocomputer for real time processing with reconfiguration network.
최흥문,김선종 대한전자공학회 1994 ISPACS:Intelligent Signal Processing and Communica Vol.1 No.1
This paper proposes an efficient parallel BP(back propagation) for large scale training-sets, and its implementation on the multicomputer system. The proposed model maps the PTS(partial training-set) into the interdependent one by introducing a modified HopfieId neural network onto the output side of BP. From the information of dependent set of patterns, we can obtain the complete energy function for the CTS(complete training-set). Also, due to the complete algorithm of the proposed scheme, the convergence problem usually met in parallel implementation can be solved regardless of the number of processors in the multicomputer. Thus, it is efficient for the larger number of patterns to be learned rapidly into the multilayer neural network. We implement the proposed model on the Transputer system connected in ring, and the results show that we can obtain the shorter convergence time, and thereby the higher speedup than the conventional BP.
병렬처리시스템에서의 최적태스크할당을 위한 Simulated Annealing알고리즘
최흥문,최봉열,박용석,김진호 경북대학교 전자기술연구소 1990 電子技術硏究誌 Vol.11 No.1
An optimal task allocation method using simulated annealing is proposed for parallel processing systems. We proposed a new cost function which is a weighted sum of 1/Sp and Ta to optimize the task allocations for parallel processing systems. where Sp is speed up factor and Ta is turnaround time. The proposed method leads to an optimal solution within resonable time by using a node grouping and efficient cost caculation. Simulation results show that this method can be easily extended to cover the many-node problems.
최흥문 대한전자공학회 1977 전자공학회지 Vol.14 No.6
This paper proposes a simple and systematic method for the generation of the fault detection test sets for the combinational logic networks. Based on tile path sensitizing concept, the test patterns for the primary input gates of the network are defined, and then it is shown that, arranging these predefined test patterns according to the path sensitizing characteristics of the given network sturctures, the minimal complete test sets for the fan-out free combinational networks can be found easily. It is also shown that, taking into account the fan-out paths sensitizing compatibility, the proposed method can be extended to the irredundant reconvergent fan-out networks.
최흥문,김진호 경북대학교 전자기술연구소 1988 電子技術硏究誌 Vol.9 No.1
This paper proposes a realistic performance evaluation technique for the parallel MIMD multimicrocomputer system. We precepts an optimal task allocation and an optimal path allocation algorithm for the multimicrocomputer systems, and after each optimization, the magnum performances are evaluated thereby. This performance evolution technique is more accurate than the conventional techniques because it takes into account the queueing delays due to the link contention in multimicrocomputer networks with limited communication bandwidth. The proposed algorithms can also be used as a design tools for dedicated multimicrocomputer system.
트랜스퓨터를 이용한 후향전파 알고리듬의 효과적인 병렬구현
최흥문,김계경,김성완,김진호 경북대학교 전자기술연구소 1993 電子技術硏究誌 Vol.14 No.1
An efficient parallel implementation of a backpropagation by using Transputer is proposed. Pattern recognition using backpropagation can be decomposed into hierarchical decompositions including network decomposition and training-set decomposition. The hierarchically decomposed parallel processing models are implemented on the Transputer system with 8 nodes, and it is applied to the recognition of 26 English capital letters with 5×6 pattern size. Experimental results show that the speedups obtained by using the network-decomposed, the training-set-decomposed, and the hierarchically decomposed model are 6.04, 5.03, and 5.74, respectively. It means that, for this specific problem size, network decomposition provides the best performance as predicted in the performance evaluation. And the analytical performance evaluation model, proposed in this paper, shows that when the problem size is extremely large, the speedup of each implementation depends, in the extreme, on whether the problem size is pattern-size intensive or pattern-quantity intensive.