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최병윤 東義大學校 産業技術開發硏究所 1999 産業技術硏究誌 Vol.13 No.-
In this paper EPR-4 viterbi decoder for magnetic disk read channel is designed. The viterbi decoder consists of ACS circuit, path memory circuit, minimum detection circuit, and output selection circuit. In the viterbi decoder the number of state is reduced from 8 to 6 using (1,7) RLL codes and modulo comparison based on 2'5 complement arithmetic is applied to handle overflow problem of ACS module. Also to determine the correct symbol values in nonconvergent condition of path memory, pipelined minimum detector which determines path with minimum state metric is used. The EPR-4 viterbi decoder is designed using MOSIS 0.35㎛ CMOS technology and consists of about 15,300 transistors and has 250 Mbps data rates under 3.30 volts.
TCP/IP프로토콜 스택을 위한 RISC 기반 송신 래퍼 프로세서 IP 설계
최병윤,장종욱 한국정보통신학회 2004 한국정보통신학회논문지 Vol.8 No.6
본 논문은 TCP/IP 프로토콜 스택을 위한 RISC 기반 송신 래퍼 프로세서의 설계를 기술하였다. 설계된 프로세서는 이중 뱅크 구조를 갖는 입출력 버퍼, 32 비트 RISC 마이크로프로세서, 온라인 체크섬 계산 기능을 갖는 DMA 모듈, 메모리 모듈로 구성되어 있다. TCP/IP 프로토콜의 다양한 동작모드를 지원하기 위해 기존의 상태 머신 기반의 설계 방식이 아닌 RISC 프로세서에 기반을 둔 하드웨어-소프트웨어 공동설계 설계기법이 사용되었다. 데이터 전달 동작과 체크섬 동작의 순차적인 수행에 기인한 커다란 지변 시간을 제거하기 위해, 데이터 전달 동작과 병렬적으로 체크섬 동작을 수행할 수 있는 DMA 모듈이 채택되었다. 가변 크기의 입출력 버퍼를 제외한 프로세서는 0.35${\mu}m$ CMOS 공정 조건에서 약 23,700개의 게이트로 구성되며, 최대 동작 주파수는 약 167MHz를 가짐을 확인하였다. In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.
최병윤,이종형,Choi Byeong-Yoon,Lee Jong-Hyoung 한국정보통신학회 2005 한국정보통신학회논문지 Vol.9 No.8
본 논문에서는 암호 기능과 함께 데이터 인증 기능을 지원하는 OCB(offsetest codebook)-AES(advanced encryption) 암호 알고리즘을 VLSI로 설계하고 성능을 분석하였다. OCB-AES 암호 알고리즘은 기존 암호 시스템에서 암호 알고리즘과 인증에 구별된 알고리즘과 하드웨어를 사용함에 따른 많은 연산 시간과 하드웨어 문제를 해결하였다. 면적 효율적인 모듈화된 오프셋 생성기와 태그 생성 회로를 내장한 OCB-AES 프로세서는 IDEC 삼성 0.35um CMOS 공정으로 설계되었으며 약 55,700 게이트로 구성되며, 80MHz의 동작주파수로 930 Mbps의 암${\cdot}$복호율을 갖는다. 그리고 무결성과 인증에 사용되는 128 비트 태그를 생성하는데 소요되는 클록사이클 수는 (m+2)${\times}$(Nr+1)이다. 여기서 m은 메시지의 블록 수이며, Nr은 AES 암호 알고리즘의 라운드 수이다. 설계된 프로세서는 높은 암${\times}$복효율과 면적 효율성으로 IEEE 802.11i 무선 랜과 모바일용 SoC(System on chip)에 암호 처리를 위한 소프트 IP(Intellectual Property)로 적용 가능하다. In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.
Application of Next Generation Sequencing Upon the Molecular Genetic Diagnosis of Deafness
최병윤,김봉직 대한청각학회 2012 Journal of Audiology & Otology Vol.16 No.1
The main objective of this review is to describe the new sequencing technologies called next generation sequencing (NGS) and its utility as a molecular genetic diagnosis tool in a medical field. Sanger method has dominated the genome sequencing industry for the past 30 years since its invention in 1975. It produced first human genome and still remains the gold standard for genome sequencing. However, it cannot meet the needs for enormous genetic data gathering and process because of its relatively long sequencing time and high cost per sample. NGS which parallelise the sequencing process, thereby increasing processing speed at a reduced cost per sample emerged to compensate for the weakness of the previous method. Currently NGS is used in some medical areas and its use is being widened. NGS also plays an important role in a study of genetically heterogenous hearing diseases. NGS is expected to mark a significant milestone in genomic research filed in a near future.
최병윤,전성환,이등호,방정환 대한이비인후과학회 2006 대한이비인후과학회지 두경부외과학 Vol.49 No.11
Keloids are fibrous overgrowth resulting from abnormal wound healing processes at the site of cutaneous injury. It extendsbeyond the confines of the original wound, begins later after injury, and does not regress with time contrary to hypertrophic scar.The gold standard has not been established in the treatment of keloids, yet. Excision of keloid alone showed a high rate ofrecurrence (45-100%). Recently, we have experienced two keloidal masses in the auricle (one on helix, the other on lobule),which were treated with surgery and adjuvant steroid injection. We developed an anteriorly-based skin flap from the skincovering of the keloidal mass and used it for several reasons. We also used triamcinolone injection after the surgery. In this paper,we are presenting the result of these cases with a review of literature. (Korean J Otolaryngol 2006;49:1104-8)