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SiO<sub>2</sub>/Si<sub>3</sub>N<sub>4</sub> 터널 절연악의 적층구조에 따른 비휘발성 메모리 소자의 특성 고찰
조원주,Cho, Won-Ju 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.1
The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated for nonvolatile memory device applications. The band structure of band-gap engineered tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with the conventional tunneling $SiO_2$ barrier. The band-gap engineered tunneling barriers composed of thin $SiO_2$ and $Si_3N_4$ layers showed a lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.
조원주 한국물리학회 2007 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.51 No.III
The solid-phase diffusion (SPD) process, which is suitable for the fabrication of fin field-effect-transistors (FinFETs) with gate length sub-100 nm, was developed for formation of ultra-shallow and abrupt $n^+$-$p$ junctions. Arsenic-doped spin-on-glass (SOG) or phosphorus-doped SOG films were used as $n$-type dopant sources, and rapid thermal annealing (RTA) was performed to diffuse dopants to the source/drain extensions of FinFETs. Arsenic-doped SOG showed a more abrupt doping profile, a higher doping concentration at the surface, and a shallower junction depth than phosphorus-doped SOG. $N^+$-$p$ junction diodes fabricated by the SPD process showed ideal one-sided abrupt-junction properties. Especially, FinFETs with a gate length of 20 nm were successfully fabricated by using the arsenic-SPD process to control the lateral source/drain junction depth and showed excellent short-channel properties.
Bias Stress Instability of Double-Gate a-IGZO TFTs on Polyimide Substrate
조원주,안민주 한국물리학회 2017 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.71 No.6
In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.
불순물 활성화 열처리가 MOS 캐패시터의 게이트 전극과 산화막의 특성에 미치는 효과
조원주,김응수 대한전자공학회 1998 電子工學會論文誌, D Vol.d35 No.10
MOS 캐패시터의 게이트 전극을 비정질 상태의 실리콘으로 형성하여 GOI(Gate Oxide Integrity)특성에 미치는 불순물 활성화 열처리의 효과를 조사하였다. LPCVD(Low Pressure Chemical Vapor Deposition) 방법으로 증착한 비정질 실리콘 게이트 전극은 활성화 열처리에 의하여 다결정 실리콘 상태로 구조가 변화하며, 불순물 원자의 활성화가 충분히 이루어졌다. 또한, 비정질 상태의 게이트 전극은 커다란 압축 응력(compressive stress)을 가지지만, 활성화 열처리 온도가 700℃에서 900℃로 증가함에 따라서 응력이 완화되었고 게이트 전극의 저항도 감소하는 특성을 보였다. 또한 얇은 게이트 산화막의 신뢰성 및 산화막의 계면특성은 활성화 열처리 온도에 크게 의존하고 있었다. 900℃에서 활성화 열처리를 한 경우가 700℃에서 열처리한 경우보다 산화막내에서의 전하 포획 특성이 개선되었으며, 산화막의 신뢰성이 향상되었다. 특히, TDDB 방법으로 예측한 게이트 산화막의 수명은 700℃의 열처리에서는 3×10/sup 10/초였지만, 900℃에서의 열처리에서는 2×10/sup 12/초로 현저하게 개선되었다. 그리고, 산화막 계면에서의 계면 전하 밀도는 게이트의 응력 완화에 따라서 개선되었다. The effects of dopant activation anneal on GOI (Gate Oxide Integrity) of MOS capacitor with amorphous silicon gate electrode were investigated. It was found that the amorphous silicon gate electrode was crystallized and the dopant atoms were sufficiently activated by activation anneal. The mechanical stress of gate electrode that reveals large compressive stress in amorphous state, was released with increase of anneal temperature from $700^{\circ}C$ to 90$0^{\circ}C$. The resistivity of gate electrode polycrystalline silicon film is decreased by the increase of anneal temperature. The reliability of thin gate oxide and interface properties between oxide and silicon substrate greatly depends on the activation anneal temperature. The charge trapping characteristics as well as oxide reliability are improved by the anneal of 90$0^{\circ}C$ compare to that of $700^{\circ}C$ or 80$0^{\circ}C$. Especially, the lifetimes of the thin gate oxide estimated by TDDB method is 3$\times$10$^{10}$ for the case of $700^{\circ}C$ anneal, is significantly increased to 2$\times$10$^{12}$ for the case of 90$0^{\circ}C$ anneal. Finally, the interface trap density is reduced with relaxation of mechanical stress of gate electrode.