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안세용(Seyong Ahn),김태환(Taewhan Kim) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.11
The power consumed by clock network and its portion in the system have been increasing. To mitigate this trend, a concept of LC resonant clock network was proposed and it has been studied and implemented by many research groups. Recently, a study which utilize LC resonant clock in the presence of DVFS was introduced. However, so far, the previous works have not been addressed the issue of multi-corner analysis on LC resonant clock. In this work, multi-corner analysis is applied to the LC resonant clock generated by previously proposed algorithm. In our analysis, wire and transistor variations are considered. Through ISPD 2010 bench marks and HSPICE simulation, analysis results on power consumption, global clock skew, and peak-to-peak voltage swing are presented. Compared to the typical case, about 27.5% power reduction, 13% voltage swing reduction and up to 50% skew increases are observed.