Twin-tub CMOS공정으로 제작된 서브마이크로미터 n채널 및 p채널 MOSFET의 특성

서용진,최현식,김상용,김태형,김창일,장의구 한국전기전자재료학회 1992 電氣電子材料學會誌 Vol.5 No.3

Twin-tub CMOS 공정에 의해 제작된 서브마이크로미터 채널길이를 갖는 n채널 및 p채널 MOSFET의 특성을 고찰하였다. n채널 및 p채널 영역에서의 불순물 프로파일과 채널 이온주입 조건에 따른 문턱전압의 의존성 및 퍼텐셜 분포를 SUPREM-II와 MINIMOS 4.0을 사용하여 시뮬레이션하였다. 문턱전압 조정을 위한 counter-doped 보론 이온주입에 의해 p채널 MOSFET는 표면에서 대략 0.15.mu.m의 깊이에서 매몰채널이 형성되었다. 각 소자의 측정 결과, 3.3[V] 구동을 위한 충분한 여유를 갖는 양호한 드레인 포화 특성과 0.2[V]이하의 문턱전압 shift를 갖는 최소화된 짧은 채널 효과, 10[V]이상의 높은 펀치쓰루 전압과 브레이크다운 전압, 낮은 subthreshold 값을 얻었다.

A Study on the Electrochemical and the Chemical Mechanical Polishing Behaviors of W and Ti Film

서용진,Sung-Woo Park 한국물리학회 2007 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.50 No.3

In this paper, the chemical mechanical polishing (CMP) performances of tungsten (W) and titanium (Ti) films according to the oxidizer content were studied through an electrochemical corrosion analysis. In order to investigate the electrochemical polishing behavior of the W and the Ti films, we used an alumina (Al$_2$O$_3$)-based tungsten slurry with a H$_2$O$_2$ oxidizer for CMP test. As an experimental result, for the case of 5 vol\% added oxidizer, the removal rates were improved, and a good polishing selectivity of 1.4 : 1 was obtained, which means that the oxidizer with the highest removal rate has a high dissolution rate due to the predominant electrochemical corrosion effects. Therefore, we conclude that the CMP characteristics of W and Ti strongly depend on the amounts of H$_2$O$_2$ oxidizer added

실리카 연마제가 첨가된 재활용 슬러리를 사용한 2단계 CMP 특성

서용진,이경진,최운식,김상용,박진성,이우선 한국전기전자재료학회 2003 전기전자재료학회논문지 Vol.16 No.9

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of roused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity (WIWNU) wore measured as a function of different slurry composition. As an experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt% contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows , In tile first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saying of high costs of slurry.

실리콘 양자전자소자의 전류-전압 및 컨덕턴스 특성

서용진 한국전기전자학회 2019 전기전자학회논문지 Vol.23 No.3

The silicon-adsorbed oxygen(Si-O) superlattice grown by ultra high vacuum-chemical vapor deposition(UHV-CVD)was introduced as an epitaxial barrier for silicon quantum electron devices. The current-voltage (I-V) measurementresults show the stable and good insulating behavior with high breakdown voltage. It is apparent that the Si-Osuperlattice can serve as an epitaxially grown insulating layer as possible replacement of silicon-on-insulator(SOI). Thisthick barrier may be useful as an epitaxial insulating gate for field effect transistors(FETs). The rationale is that itshould be possible to fabricate a FET on top of another FET, moving one step closer to the ultimate goal of futuresilicon-based three-dimensional integrated circuit(3DIC). 초고진공 화학기상증착장치(UHV-CVD)에 의해 성장된 실리콘-흡착된 산소(Si-O) 초격자가 실리콘 양자전자소자를 위한에피택셜 장벽으로 소개되었다. 전류-전압 측정 결과 높은 브레이크다운 전압을 갖는 매우 안정하고 양호한 절연특성을 나타내었다. 에피택셜 성장된 Si-O 초격자는 SOI(silicon on insulator)를 대체할 수 있는 절연층으로도 사용될 수 있음을 보여준다. 이 두꺼운 장벽은 전계효과트랜지스터(FET)의 절연 게이트로 유용하게 사용될 수 있어 FET 위에 또 다른 FET를 제작할 수 있으므로 미래 실리콘계 3차원 집적회로의 궁극적인 목표에 한층 더 다가갈 수 있는 가능성을 보여주는 것이다.

HSS STI-CMP적용을 위한이중 패드의 최적화

서용진,박성우,김철복,정소용,이경진,김기욱,박창준 대불대학교 2002 大佛大學校大學院 硏究論文集 Vol.- No.1

As the device geometry shrinks to the deep submicron region, chemical mechanical polishing(CMP) planarization become a more essential technique of advanced ULSI process. Also, CMP process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric(ILD) layers and interconnections with free-defect. Especially, the complete global planarization of IMD, ILD and interconnections can be achieved only with the CMP process. However, as the IMD and ILD layer gets thinner, several problems were found in the CMP process. It does have various problems such as dishing effect, torn oxide defects and nitride residues in oxide. So, it leads to severe circuit failure, which affects yield. In this paper, we studied the characteristics of polishing pad, which can apply STI-CMP process for global planarization of multilevel interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was defected less than 2 on JR111 pad. Through the above result, we can select optimum polishing pad, so we can expect the improvement of throughput and device yield.

물류이동거리 최소를 위한 유전자 알고리즘 기반 FAB Facility 배치

서용진,최진영 한국산업경영시스템학회 2016 한국산업경영시스템학회 학술대회 Vol.2016 No.추계

컴퓨터 시뮬레이션에 의한 서브마이크론 CMOS 소자의 디자인 고려사항

서용진 대불대학교 1996 論文集 Vol.2 No.2

In the manufacturing of VLSI circuits, variations of device characteristics due to the slight differences in process parameters drastically aggravate the performance of fabricated devices. Therefore, it is very important to establish optimal process conditions in order to minimize device sensitivities. In this paper, we used one-dimensional process simulator, SUPREM-Ⅱ, and two-dimensional device simulator, MINIMOS 4.0 in ordr to extract optimal process parameter which can minimize changes of the device characteristics caused by process parameter variation in the case of submicron CMOS devices. From this simulation, we have discussed design considerations from the dependences between process parameters and device characteristics.

표면이온주입에 의한 LDD-nMOSFET의 핫 캐리어 신뢰성 개선에 대한 연구

서용진 대불대학교 1998 論文集 Vol.4 No.1

Reduction of hot carrier degradation in MOS devices has been one of the most serious concerns for MOS-ULSIs. In this paper, three types of LDD structure for suppression of hot carrier degradation, such as spacer-induced degradation and decrease of performance due to increase of series resistance will be investigated. LDD-nMOSFETs used in this study had three different drain structure, (1) conventional Surface type LDD(SL), (2) Buried type LDD(BL), (3)Surface Implantation type LDD(SI). As a results, the surface implantation type LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structure.

반도체-원자 초격자의 광전자 특성

서용진,정소영,박성우 대불대학교 2002 論文集 Vol.8 No.1

Optoelectronic characteristics of the superlattice as a function of deposition temperature and annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy (MBE) system. Consequently, the experimental results of superlattice with multilayer Si-O structure showed the stable photoluminescence(PL) and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic and quantum device as well as for the replacement of silicon-on-insulator(SOI) in ultra high speed and lower power CMOS devices in the future, and it can be readily integrated with silicon ULSI processing.

Epitaxially Grown Multilayer Nanocrystalline Si-O Structure for Silicon-on-Insulator Applications

서용진,R.Tsu 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.45 No.1

In this paper, monolayers of oxygen atoms are sandwiched between adjacent epitaxial silicon layers fabricated in order to investigate the possible replacement of silicon-on-insulator (SOI) for nano- CMOS (complementary metal-oxide semiconductor) devices of a future generation. This multi-layer Si-O superlattice forms a new type of superlattice, a semiconductor-atomic superlattice (SAS). According to the experimental results, cross-sectional high-resolution transmission electron microscopy (HRTEM) shows the epitaxial system. Also, the current-voltage (I-V) measurement results show a stable and good insulating behavior, with high breakdown voltage. It is apparent that the system may form an epitaxially-grown insulating layer as a possible replacement for SOI, a scheme investigated as a future generation of high-eciency and high-density CMOS on SOI. Since our scheme is epitaxial, three-dimensional integrated circuits (3D-ICs) may nally be realized in silicon-based technology.