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金商奎 啓明大學校 産業經營硏究所 1987 經營經濟 Vol.20 No.1
Regarding the nature. of tax incidence, a general tax on consumption tends to be regressive. The reason is that consumption outlays as a percentage of income tend to be fall as we move up the income scale. This explains why in the historical development, income taxation has been identified with progressive taxation and sales taxes with regressive taxation. The income tax has developed in the framework of personal taxation, while consumption taxes has been locked into the vice of the impersonal or in rem approach of sales taxation. Resort to a personal type of expenditure tax would break this bondage and permit the taxation of consumption to be based on a personal and progressive basis. Thereby, personal expenditure tax(P.E.T.) would make a contribution to an equity efficiency and maximum of tax revenue. However, it remains to explore some of the technical problems involved in app1ying P. E.T.: problems of administration, consumers' capital expenditure, treatment of gifts and requests, treatment of the family and the transition. In accordance, it might be impossible to think of replacing the present system with a P.E.T. system at one stroke. There is well over a hundred years' accumulated experience in administring the income tax. There is no such experience concerning the P.E.T. Therefore, in this paper specifically in ChapterⅡ, I have explored the theoretical background in relation to taxation method of P.E.T. Also, I have analyzed the saving increase effect, avoiding the risk in investment, raising the worker's incentive with this tax system and economic control of P.E.T. in ChapterⅢ. In ChapterⅣ, I considered the examination of applicability, the problems and impediment of P.E.T. Finally, in ChapterⅤ, I surveyed the summary of this paper and the prospect of P.E.T system.
PLL을 이용한 고속 마이크로프로세서용 32MHz~1GHz 광대역 클럭발생회로
김상규,이재형,이수형,정강민,Kim, Sang-Kyu,Lee, Jae-Hyung,Lee, Soo-Hyung,Chung, Kang-Min 한국정보처리학회 2000 정보처리논문지 Vol.7 No.1
This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW. 본 연구에서 PLL을 이용한 고속 마이크로프로세서용 클럭발생회로를 설계하였다. 이 회로는 32MHz${\sim}$1GHz 클럭을 발생시키며 마이크로프로세서내에 내장될 수 있다. 동적 차동래치를 사용하여 고속 D Flip-Flop을 설게하였고 이에 의거한 새로운 형태의 위상주파수 검출기를 제시하였다. 이 검출기는 위상민감도오차가 매우 적으며 이를 사용한 PLL은 위상오차가 적은 우수한 위상특성을 지닌다. 또한 전압제어발진기 VCO의 선형적 제어를 위하여 전압-전류 변환기가 구동하는 전류제어 발진기로 구성된 새로운 구조의 VCO를 제시하였다. 이러한 PLL에서 제어전압 범위를 1V${\sim}$5V로 넓히고 발생클럭의 주파수를 32 MHz${\sim}$1 GHz로 증가시킬 수 있었다. 클럭발생회로는 $0.65\;{\mu}m$ CMOS 기술을 이용하여 설계하였다. 이 회로는 $1.1\;{\mu}s$의 lock-in 시간과 20mW 이하의 전력소비를 갖는다.