게르마늄 Prearmophization 이온주입을 이용한 티타늄 salicide 접합부 특성 개선

김삼동,이성대,이진구,황인석,박대규,Kim, Sam-Dong,Lee, Seong-Dae,Lee, Jin-Gu,Hwang, In-Seok,Park, Dae-Gyu 한국재료학회 2000 한국재료학회지 Vol.10 No.12

본 연구에서는 Ge PAM이 선폭 미세화에 따른 C54 실리사이드화 및 실제 CMOS 트랜지스터 접합부에서의 각종 전기적 특성에 미치는 영향을, As PAM과의 비교를 통하여 관찰하였다. 평판 상에서 각 PAM 및 기판의 도핑 상태에 따른 Rs의 변화량을 측정하였으며, 각 PAM 방식은 기존의 살리사이드 TiSi$_2$에 비해 개선된 C54 형성 효과를 보였다. 특히, Ge PAM은 n+ 기판에서 As PAM보다 효과적인 실리사이드화를 보였고, 이 경우 XRB 상에서도 가장 강한 (040) C54 배향성을 나타내었다. ~0.25$\mu\textrm{m}$ 선폭 및 n+ 접합층에서 기존 방식에 비해 As과 Ge PAM은 각각 ~85,66%의 개선된 바저항을 보였으며, P+ 접합층에서는 As과 Ge PAM 모두 62~63% 정도의 유사한 Rs 개선 효과를 보였다. 콘택 저항에서도 각 콘택 크기 별로 바저항(bar resistance) 개선과 같은 경향의 PAM 효과를 관찰하였으며, 모든 경우 10 $\Omega$/ct. 이하로 양호한 결과를 보였다. 누설 전류는 area 형 패턴에서는 모든 공정 조건에서 <10E-14A/$\mu\textrm{m}^{2}$ 이하로, edge 형에서는 특히 P+ 접합부에서 As 또는 Ge PAM 적용 시 <10E-13 A/$\mu\textrm{m}^{2}$ 이하로 다소 누설 전류를 안정화시키는 결과를 보였다. 이러한 결과는 XTEM에 의해 관찰된 바 Ge PAM 적용 시 기존의 경우에 (PAM 적용 안한 경우) 비해 유사한 평활도의 TiSi$_2$박막 형상과 일치하였으며, 또한 본 실험의 Ge PAM 이온주입 조건이 접합층에 손상을 주지 않는 범위에서 적정화되었음을 제시하였다 We studied the effects of Ge preamorphization (PAM) on 0.25$\mu\textrm{m}$ Ti-salicide junctions using comparative study with As PAM. For each PAM schemes, ion implantations are performed at a dose of 2E14 ion/$\textrm{cm}^2$ and at 20keV energy using $^{75}$ /As+and GeF4 ion sources. Ge PAM showed better sheet resistance and within- wafer uniformity than those of As PAM at 0.257m line width of n +/p-well junctions. This attributes to enhanced C54-silicidation reaction and strong (040) preferred orientation of the C54-silicide due to minimized As presence at n+ junctions. At p+ junctions, comparable performance was obtained in Rs reduction at fine lines from both As and Ge PAM schemes. Junction leakage current (JLC) revels are below ~1E-14 A/$\mu\textrm{m}^{2}$ at area patterns for all process conditions, whereas no degradation in JLC is shown under Ge PAM condition even at edge- intensive patterns. Smooth $TiSi_2$ interface is observed by cross- section TEM (X- TEM), which supports minimized silicide agglomeration due to Ge PAM and low level of JLC. Both junction break- down voltage (JBV) and contact resistances are satisfactory at all process conditions.

고 indium 농도 InGaAs와 GaAs 박막간 계면에 관한 연구

김삼동,Kim, Sam-Dong 한국재료학회 1996 한국재료학회지 Vol.6 No.1

분자선 증착법(Molecular Beam Epitaxy)에 의하여 성장시킨 고농도 InGaAs layer에서 성장중지법이 계면 거칠기에 미치는 영향이 연구되었다. 계면을 평활화하기 위하여 단원자층의 GaAs 또는 AIAs를 InGaAs alyer 양쪽 계면에 증착한 뒤 뒤이어 성장중지를 실시하였다. Photoluminescence(PL) 측정에 의하면, 단원자 GaAs층 증착을 통한 평활화법보다 상당히 향상된 계면조건을 보여졌다. 고 분해능 단면 전자현미경법(Cross-section high resolution transmission electron microscopy, XHRTEM)에 의해 관찰되어진바, 계면 평활화법에 의해 계면의 평활성, 연속성 및 결정결함 밀도등에서 현저한 향상이 얻어졌다.

Stress Concentration Effects on the Nucleation of the Structural Defects in Highly Strained Heteroepitaxial Layers

김삼동,이진구,Kim, Sam-Dong,Lee, Jin-Koo Materials Research Society of Korea 2001 한국재료학회지 Vol.11 No.7

본 연구에서는 고변형된 이중 에피층에서 두 가지 종류의 반원 전위 루프 ($60^{\circ}$및 쌍격자 전위)의 생성 속도물 예측하는 모델을 제안한다. 모델링 시, 에피층 표면에서 발생하는 결함과 이곳에 집중되는 응력 효과를 고려하였으며, Matthew의 식을 발전시켜 에피층 두께에 따른 잔류 변형율을 변수로 사용하였다. 모델링을 통한 계산 결과에 의하면, 응력 집중 현상은 고변형된 이종에피층에서 전위 및 결정 결함 현상을 설명하는 데 매우 중요하였다. 또한,본 연구를 퉁하여, 응력 집중 현상이 에피층 성장 초기에 생성되는 전위 형태를 결정하는 주요한 인자 중 하나임을 단면 투과 전자 현미경 결과와의 비교를 통해 확인할 수 있었다. We carried out the kinetic model calculations in order to estimate the nucleation rates for two kinds of half-loop dislocations in highly strained hetero-epitaxial growths; $60^{\circ}$dislocations and twinning dislocations. The surface defects and the stress concentration effects were considered in this model, and the remaining elastic strain of the epilayers with increasing film thickness was taken into account by using the modified Matthews' relation. The calculations showed that the stress concentration effect at surface imperfections is very important for describing the defect generation in highly mismatched epitaxial growth. This work also showed that the stress concentration effect determined the type of dislocation nucleating dominantly at early growth stages in accordance with our XTEM (cross-section transmission electron microscopy) defect observation.

Thermal stabilities of metal bottom electrodes for Ta2O5 metal-oxide-metal capacitor structure

김삼동 한국물리학회 2007 Current Applied Physics Vol.7 No.2

Thermal stabilities of various metal bottom electrodes were examined by using a Ta2O5 metal-oxide-metal (MOM) capacitor struc-ture. After depositing 10-nm thick Ta2O5 on metal-electrode/poly-Si, we performed rapid thermal oxidation (RTO) at 850.C for 60 s inan O2 ambient. A chemical-vapor-deposition (CVD) WSi2 electrode showed satisfactory thermal stability after the RTO, while otherexamined electrode materials exhibited thermal degradation caused by oxidation failure or interfacial reaction between the substratepoly-Si and the Ta2O5. After post-annealing at 650.C for 30 min (in N2 condition) with CVD TiN top electrode, an eective oxide thick-ness (Tox) o f. 32 A˚and a leakage current density of. 107 A/cm2 at 1.25 V were obtained from the MOM capacitor with the WSi2 bot-tom electrode. Other electrode materials, such as TiN, TiSix, W Nx, W, and Ta, were severely oxidized during the RTO in the MOMstructures, and very poor capacitor properties were obtained in terms ofTox and leakage current.

[밀리터리파 분야] 밀리미터파 능동 소자 및 MMIC 개발과 제작 공정

김삼동,박현창,이진구,오정훈 한국전자파학회 2008 전자파기술 Vol.19 No.5

Analysis of the Short-Channel Eect in 50 nm InAlAs/InGaAs Metamorphic High Electron Mobility Transistors

김삼동,이진구,임병옥,오정훈,이재서 한국물리학회 2008 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.53 No.6

We fabricate 50-nm InAlAs/InGaAs metamorphic high electron mobility transistors and investigate the short-channel effect by using a numerical analysis based on the hydrodynamic model. Our numerical approach is validated by comparing the computed values with the I-V characteristics measured from the fabricated devices at various bias conditions. From the analysis, we propose two different causes for the short-channel effect, depending on the gate bias condition. At small gate voltages of 0 ∽ -0.3 V, overflow of hot-electrons from the channel toward the buffer layers contribute to the non-zero output conductance at high Vds and the amount of this current component is quite significant and ∽1/6 the peak current density in the channel at a drain voltage of 1.6 V. At a higher gate voltage of -0.6 V, drain-induced barrier lowering plays a role in the significant increase of the output conductance above a drain voltage of 0.5 V. We fabricate 50-nm InAlAs/InGaAs metamorphic high electron mobility transistors and investigate the short-channel effect by using a numerical analysis based on the hydrodynamic model. Our numerical approach is validated by comparing the computed values with the I-V characteristics measured from the fabricated devices at various bias conditions. From the analysis, we propose two different causes for the short-channel effect, depending on the gate bias condition. At small gate voltages of 0 ∽ -0.3 V, overflow of hot-electrons from the channel toward the buffer layers contribute to the non-zero output conductance at high Vds and the amount of this current component is quite significant and ∽1/6 the peak current density in the channel at a drain voltage of 1.6 V. At a higher gate voltage of -0.6 V, drain-induced barrier lowering plays a role in the significant increase of the output conductance above a drain voltage of 0.5 V.

Low dielectric constant spin-on-glass passivation for high speed complementary metal oxide silicon devices

김삼동 한국물리학회 2003 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.43 No.I

We examined the eects of the non-etchback passivation process using a low dielectric constant (r) methylsilsesquioxane spin-on-glass (SOG) on the electrical characteristics of high-speed Si-based memory devices which are very sensitive to the parasitic coupling capacitance among the interconnection metal lines. The pass rate ratio of the fully functional on-wafer chips strongly depends on the dielectric constants, as well as on the local planarization, of SOG materials consisting of passivation structures deposited over the second metal lines. When low r (2.7) methylsilsesquioxane SOG of a 6600 A as-coated thickness is used for the passivation, a relative pass rate ratio of 92 % is obtained. This pass rate is almost comparable with the device yield of unpassivated chips (eective dielectric constant = 1) and is much higher than that (62 %) of chips passivated by using the conventional oxide/silicon-nitride structures. Compared to the conventional passivation structures, no signicant shift in threshold voltage is observed in either active or eld transistors with low r SOG-based passivation structures, which suggests no electrical side eect on the metal-oxide-silicon transistors due to the methylsilsesquioxane SOG chemicals. We examined the eects of the non-etchback passivation process using a low dielectric constant (r) methylsilsesquioxane spin-on-glass (SOG) on the electrical characteristics of high-speed Si-based memory devices which are very sensitive to the parasitic coupling capacitance among the interconnection metal lines. The pass rate ratio of the fully functional on-wafer chips strongly depends on the dielectric constants, as well as on the local planarization, of SOG materials consisting of passivation structures deposited over the second metal lines. When low r (2.7) methylsilsesquioxane SOG of a 6600 A as-coated thickness is used for the passivation, a relative pass rate ratio of 92 % is obtained. This pass rate is almost comparable with the device yield of unpassivated chips (eective dielectric constant = 1) and is much higher than that (62 %) of chips passivated by using the conventional oxide/silicon-nitride structures. Compared to the conventional passivation structures, no signicant shift in threshold voltage is observed in either active or eld transistors with low r SOG-based passivation structures, which suggests no electrical side eect on the metal-oxide-silicon transistors due to the methylsilsesquioxane SOG chemicals.

Thermal stability of diffusion barriers for storage node electrode structures of Si-based memory devices

김삼동 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.45 No.2

We examine the thermal stabilities of a variety of diusion barriers for the storage-node bottom electrode structures of Si-based memory devices in an oxygen ambient condition. For the comparative study, O2-stued sputtered TiN, WNx and TiCl4-based TiN deposited by chemical vapor deposition (CVD) and sputtered TiAlN diusion barriers are used with Pt or Ir electrodes. Among the electrode structures used in this study, the sputter TiAlN barrier/Pt structure shows the best thermal stability, exhibiting neither structural collapse nor surface hillocks at 700 C in O2, and those structures are even stable at 750 C in a N2 ambient. The TiN or WNx barrier deposited either by using CVD, which has superior lm step coverage, or by using the sputtering method with the use Pt electrodes shows early oxidation failure at 500 600 C in O2. The CVD TiN/Ir structure is stable up to 700 C with no distinctive oxidation in the barrier or reaction due to inter-diusion between the Ir electrode and the poly-Si underlayer; however, many surface hillocks are formed on the Ir surfaces above at 600 C, which is thought be due to surface oxidation of Ir. The excellent thermal stability of the TiAlN barrier/Pt structure during O2 annealing is thought to be due to the early formation of a very thin AlOx layer that retards any further oxidation of TiSi2.

전기설비의 안전보호장치(2)

김삼동 대한전기협회 1981 대한전기협회지 Vol.- No.56

Microstructural properties of plasma-enhanced chemical vapor deposited WNx films using WF6-H2-N2 precursor system

김삼동 한국물리학회 2007 Current Applied Physics Vol.7 No.4

AWF6H2N2 x lms. We examined themicrostructural changes of the WNx lms depending on N2/H2 ow-rate ratio and post-annealing (600800.C for 1 h). As the N2/H2 owrate was increased from 0 to 1.5, as-deposited WNx lms exhibited various dierent crystalline states, such as nanocrystalline and/oramorphous structure comprising W, WN, and W2N phases, a ne W2crystalline structure ofb-W2N phase. After post-annealing above 600.C, crystalline recovery with phase separation tob-W2N anda-W was observed from the WNx lms deposited at an optimized deposition condition (ow-rate ratio = 0.25). From this PECVDmethod, an excellent step coverage of. 90% was obtained from the WNx lms at a contact diameter of 0.4l m and an aspect ratio of 3.5.