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Vertically Integrated Multiple Nanowire Field Effect Transistor
Lee, Byung-Hyun,Kang, Min-Ho,Ahn, Dae-Chul,Park, Jun-Young,Bang, Tewook,Jeon, Seung-Bae,Hur, Jae,Lee, Dongil,Choi, Yang-Kyu American Chemical Society 2015 NANO LETTERS Vol.15 No.12
<P>A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/nalefd/2015/nalefd.2015.15.issue-12/acs.nanolett.5b03460/production/images/medium/nl-2015-034602_0007.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/nl5b03460'>ACS Electronic Supporting Info</A></P>
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Vertically Integrated Nanowire-Based Unified Memory
Lee, Byung-Hyun,Ahn, Dae-Chul,Kang, Min-Ho,Jeon, Seung-Bae,Choi, Yang-Kyu American Chemical Society 2016 Nano letters Vol.16 No.9
<P>A vertically integrated nanowire-based device for multifunctional Unified, memory that combine dynamic random access memory (DRAM) and flash memory,,in a single transistor is demonstrated for the first time. The:device Utilizes a gate-all-around (GAA) structure that completely surrounds the nano-wire; the structure is built on a-bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) reliable reproducibility, stiction-free stability, and high-uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified-memory (UM) characteristics. In addition-to-each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing Memory window-than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications.</P>
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A Vertically Integrated Junctionless Nanowire Transistor
Lee, Byung-Hyun,Hur, Jae,Kang, Min-Ho,Bang, Tewook,Ahn, Dae-Chul,Lee, Dongil,Kim, Kwang-Hee,Choi, Yang-Kyu American Chemical Society 2016 NANO LETTERS Vol.16 No.3
<P>A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.</P>
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