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Secure Wireless Body Area Network (WBAN) Communication Method Using New Random Key Management Scheme
Reza Khalilian,Abdalhossein Rezai,Farhad Mesrinejad 보안공학연구지원센터 2016 International Journal of Security and Its Applicat Vol.10 No.11
Wireless Body Area Networks (WBANs) have an important role in healthcare. So, the security of WBANs becomes a challenging issue. High performance encryption method and efficient key management scheme are required for securing WBAN communications. This study presents and evaluates an efficient key management scheme and efficient encryption method for improving WBAN security. We proposed a new random key management scheme. The proposed method utilized Advanced Encryption Standard (AES)-256 to encrypt the bio signals. Simulation results show that the proposed method has advantages compared to other secure WBAN communication methods.
A Novel Low Power and Low Voltage Bulk-Input Four-Quadrant Analog Multiplier in Voltage Mode
Sheema Soltany,Abdalhossein Rezai 보안공학연구지원센터 2016 International Journal of Multimedia and Ubiquitous Vol.11 No.1
This paper presents a new CMOS four-quadrant low voltage and low power analog multiplier circuit in voltage mode. In the proposed analog multiplier, transistors are biased in weak inversion by driving them at bulk terminals. The proposed design has fully differential ended output. Input signal ranges are ±40mV and all transistors have the equal sizes. Simulation results have been presented by HSPICE simulator in 0.18μm standard CMOS technology to confirm the operation of the circuit. The results show that the proposed analog multiplier has several advantages in comparison with other analog multipliers.
Design and Evaluation of Novel Effective Montgomery Modular Multiplication Architecture
Maryam Moayedi,Abdalhossein Rezai 보안공학연구지원센터 2016 International Journal of Security and Its Applicat Vol.10 No.10
Secure communication is a challenging issue in modern industries and critical infrastructures. The core technology used for securing the communication is cryptography. Modular multiplication is an important operation in cryptosystems. This paper investigates a novel modular multiplication algorithm and architecture. In the proposed algorithm and architecture, the parallel architecture and compact SD technique are utilized to improve the performance of modular multiplication operation and cryptosystems. The proposed architecture is implemented on Xilinx Virtex 5 FPGA. The complexity analysis results and FPGA implementation results show that the proposed modular multiplication algorithm and architecture provide improvement on the total computation time and area×time complexity compared to other modified modular multiplication algorithms and architectures.