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    저조도 환경 대응 다중 스케일 실시간 영상 향상 및 잡음 제거 하드웨어 아키텍처 설계

    한글로보기

    https://www.riss.kr/link?id=T17550499

    • 저자
    • 발행사항

      서울 : 한국외국어대학교 대학원, 2026

    • 학위논문사항

      학위논문(석사) -- 한국외국어대학교 대학원 , 전자공학과 , 2026. 8

    • 발행연도

      2026

    • 작성언어

      한국어

    • 주제어
    • DDC

      621.381 판사항(22)

    • 발행국(도시)

      서울

    • 기타서명

      Hardware Architecture Design for Multi-Scale Real-Time Image Enhancement and Denoising in Low-Light Environments

    • 형태사항

      iv, 63 p. : 삽도 ; 26 cm

    • 일반주기명

      한국외국어대학교 논문은 저작권에 의해 보호받습니다.
      지도교수: 조경순
      참고문헌: p. 59-61

    • UCI식별코드

      I804:11059-200001012517

    • 소장기관
      • 한국외국어대학교 글로벌캠퍼스 도서관 소장기관정보
      • 한국외국어대학교 서울캠퍼스 도서관 소장기관정보
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    부가정보

    다국어 초록 (Multilingual Abstract) kakao i 다국어 번역

    Low-light image enhancement is essential for applications such as intelligent transportation and security surveillance, yet images captured under low-light conditions commonly suffer from low brightness, poor contrast, and severe noise. Existing enhancement algorithms often introduce noise amplification and color distortion when improving brightness, making it difficult to satisfy both image quality and real-time requirements simultaneously. This thesis proposes an image enhancement algorithm based on Modified CLAHE, Haar discrete wavelet transform (DWT), guided filter, and adaptive high- and low-frequency fusion, and presents a complete RTL-level hardware circuit design targeting 1920×1080 resolution. The proposed algorithm performs mild contrast enhancement on the luminance channel via Modified CLAHE, decomposes the original and enhanced luminance into high- and low-frequency subbands using Haar DWT, removes high-frequency noise with a guided filter while preserving edges, and reconstructs the enhanced luminance image through adaptive fusion based on energy and visibility weighting followed by inverse DWT. Comparison with six conventional algorithms demonstrates that the proposed method effectively suppresses noise and prevents whitening while achieving the lowest overexposure ratio and the highest signal-to-noise ratio. The circuit is designed in Verilog HDL at the RTL level and synthesized using the Yosys open-source synthesis tool with the NanGate 45 nm standard-cell library. By introducing a parameterized pipelined restoring divider, the maximum operating frequency is improved from 100 MHz to 292 MHz at the cost of approximately 22% area overhead. The final design comprises 283,569 equivalent gates and 811,132 bits of on-chip memory, achieving a throughput of 141 fps (2.35 times the 60 fps real-time requirement) for Full HD images and 35 fps for 4K resolution.
    번역하기

    Low-light image enhancement is essential for applications such as intelligent transportation and security surveillance, yet images captured under low-light conditions commonly suffer from low brightness, poor contrast, and severe noise. Existing enhan...

    Low-light image enhancement is essential for applications such as intelligent transportation and security surveillance, yet images captured under low-light conditions commonly suffer from low brightness, poor contrast, and severe noise. Existing enhancement algorithms often introduce noise amplification and color distortion when improving brightness, making it difficult to satisfy both image quality and real-time requirements simultaneously. This thesis proposes an image enhancement algorithm based on Modified CLAHE, Haar discrete wavelet transform (DWT), guided filter, and adaptive high- and low-frequency fusion, and presents a complete RTL-level hardware circuit design targeting 1920×1080 resolution. The proposed algorithm performs mild contrast enhancement on the luminance channel via Modified CLAHE, decomposes the original and enhanced luminance into high- and low-frequency subbands using Haar DWT, removes high-frequency noise with a guided filter while preserving edges, and reconstructs the enhanced luminance image through adaptive fusion based on energy and visibility weighting followed by inverse DWT. Comparison with six conventional algorithms demonstrates that the proposed method effectively suppresses noise and prevents whitening while achieving the lowest overexposure ratio and the highest signal-to-noise ratio. The circuit is designed in Verilog HDL at the RTL level and synthesized using the Yosys open-source synthesis tool with the NanGate 45 nm standard-cell library. By introducing a parameterized pipelined restoring divider, the maximum operating frequency is improved from 100 MHz to 292 MHz at the cost of approximately 22% area overhead. The final design comprises 283,569 equivalent gates and 811,132 bits of on-chip memory, achieving a throughput of 141 fps (2.35 times the 60 fps real-time requirement) for Full HD images and 35 fps for 4K resolution.

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    목차 (Table of Contents)

    • I. 서론. 1
    • 1.1 연구 배경 1
    • 1.2 연구 방법 5
    • II. 저조도 영상 향상 알고리즘 이론 7
    • I. 서론. 1
    • 1.1 연구 배경 1
    • 1.2 연구 방법 5
    • II. 저조도 영상 향상 알고리즘 이론 7
    • 2.1 저조도 영상 열화 모델 7
    • 2.2 색상 공간 변환 9
    • 2.3 개선형 CLAHE 알고리즘 11
    • 2.3.1 히스토그램 통계 및 대비 클리핑 12
    • 2.3.2 화소 재분배 및 CDF 매핑 14
    • 2.3.3 쌍선형 보간 16
    • 2.4 Haar 웨이블릿 변환 17
    • 2.4.1 Haar 정변환 17
    • 2.4.2 Haar 역웨이블릿 변환 20
    • 2.5 가이디드 필터 21
    • 2.6 이중 스트림 융합 전략 23
    • 2.6.1 고주파 서브 밴드 융합 23
    • 2.6.2 저주파 서브 밴드 융합 26
    • III. 저조도 영상 향상 하드웨어 설계 28
    • 3.1 시스템 전체 아키텍처 28
    • 3.2 CLAHE 하드웨어 설계 30
    • 3.2.1 CLAHE 모듈 전체 구조 30
    • 3.2.2 클리핑 및 CDF 생성 32
    • 3.2.3 병렬 저장 아키텍처 34
    • 3.2.4 쌍선형 보간 매핑 36
    • 3.3 Haar 웨이블릿 변환 하드웨어 설계 37
    • 3.4 가이디드 필터 하드웨어 설계 39
    • 3.5 이중 스트림 융합 하드웨어 설계 41
    • 3.5.1 융합 코어 전체 구조 41
    • 3.5.2 융합 연산 로직 43
    • 3.5.3 파이프라인 지연 정렬 46
    • IV. 실험 결과 48
    • V. 결론 57
    • 참고문헌 59
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