Structural and Electrical Characteristics of Tellurium-Based Field-Effect Devices = 텔루륨 기반 전계효과 소자의 구조 및 전기적 특성

다국어 초록 (Multilingual Abstract)

While 2D tellurium (Te) features exceptional room-temperature hole mobility dictated by its unique helical chain architecture, the realization of high-performance Te field-effect transistors (FETs) remains limited by interfacial instabilities at the contact zones. This study systematically reveals the coupled impacts of contact architecture and processing induced stress fields on the charge transport dynamics of Te devices. By replacing conventional evaporated metallization with a van der Waals (vdW) graphene contact strategy. To maintain interfacial coupling throughout processing, a polycarbonate (PC) mechanical clamping layer was introduced. Upon sacrificial chemical removal of the PC overlayer, a pronounced degradation in both contact resistance and switching performance was observed. Comparative studies utilizing h-BN passivated stacks explicitly decouple this behavior from chemical degradation, revealing instead a mechanical relaxation phenomenon that broadens the interfacial vdW gap distance. Furthermore, surface engineering through plasma enhanced chemical vapor deposition (PECVD) confirms a solid correlation between localized surface disorder and macroscopic electrical sensitivity. Our findings demonstrate that mechanical interface integrity is a primary governing factor in vdW device architectures, outlining vital design pathways for robust p-channel 2D complementary logic circuits.

목차 (Table of Contents)

• [List of Figures] i
• Chapter 1 Introduction 1
• 1.1 Evolution of Semiconductor Technology 1
• 1.1.1 Two-Dimensional Materials 4
• 1.1.2 Transition Metal Dichalcogenides (TMDCs) 8
• 1.2 Synthesis and Fabrication of 2D Devices 11
• 1.2.1 Top-Down Approaches 14
• 1.2.1.1 Mechanical Exfoliation 14
• 1.2.1.2 Liquid Phase Exfoliation 17
• 1.2.2 Bottom-Up Approaches 19
• 1.2.2.1 Chemical Vapor Deposition (CVD) 19
• 1.2.2.2 Physical vapor deposition (PVD) 22
• 1.2.2.3 Atomic Layer Deposition (ALD) 25
• 1.2.3 Fabrication Techniques 27
• 1.2.3.1 Lithography 27
• 1.2.3.2 Wet transfer 30
• 1.2.3.3 Dry transfer (PDMS/PC) 32
• 1.3 Tellurium: A Unique Quasi-2D Semiconductor 35
• 1.3.1 Crystal Structure and Electronic Properties of Tellurium 35
• 1.3.2 Thickness-Dependent Bandgap 38
• 1.4 Limitations and Stability Challenges in Tellurium Devices 40
• 1.4.1 Previously Reported Stability Enhancement Strategies 43
• 1.4.1.1 Contact Engineering via Thickness and Material Selection 43
• 1.4.1.2 Interfacial Passivation 45
• 1.4.1.3 PC-Assisted Passivation for Enhanced Tellurium FET Stability 47
• 1.5 Device Applications of 2D Materials 49
• 1.5.1 Field Effect Transistors 49
• Chapter 2 Experimental Method 51
• 2.1 Synthesis of Tellurium Crystal via PVT Method 51
• 2.2 Mechanical Exfoliation of 2D Materials 53
• 2.2.1 Graphene and h-BN Exfoliation 53
• 2.3 Transfer Process 53
• 2.3.1 Polymer Assisted Transfer Process 53
• 2.3.2 Poly(Bisphenol A carbonate) (PC) Stamp Transfer Process 54
• 2.3.3 Interface Protection and Mechanical Clamping with h-BN 57
• 2.3.4 Fabrication of Te FET Devices 57
• 2.4 PECVD Surface Modification 60
• Chapter 3 Results and Discussions 62
• 3.1 Morphology and Structural Properties of Tellurium Flakes 62
• 3.1.1 Structural Analysis of Tellurium Flakes 62
• 3.1.2 Raman and Optical Analysis of Graphene and h-BN 65
• 3.2 SEM and EDS analysis of Te-based devices 67
• 3.3 Electrical Characteristics of Te-Based Devices 70
• 3.3.1 Structural Analysis of Graphene–Te Device 72
• 3.3.2 Electrical Characteristics of Graphene-Te Devices 74
• 3.3.3 Structural Analysis of h-BN/Graphene–Te Device 77
• 3.3.4 Electrical Characteristics of h-BN/Graphene-Te Devices 79
• 3.3.5 Effect of PC Removal on Device Performance 82
• 3.4 Effect of Plasma-Enhanced Chemical Vapor Deposition (PECVD) 84
• 3.4.1 Structural Modification of Tellurium after PECVD 84
• 3.4.2 Electrical Impact of PECVD on Device Performance 87
• Chapter 4 Conclusion 90
• References 92
• Acknowledgements 100