Design and Dual Closed-Loop Control of a 2.5-kW Four-Phase Interleaved SEPIC Chopper Circuit for End-of-Life Battery Module Discharge = 폐배터리 모듈 방전을 위한 2.5kW 급4상 인터리브드 SEPIC 쵸퍼 회로 설계 및 이중 폐루프 제어에 관한 연구

국문 초록 (Abstract)

사용 후 배터리의 심방전 재활용 과정에서 넓은 안전 운전 범위, 내부저항의 비선형적인 급격한 증가, 그리고 단자전압의 급격한 저하와 같은 문제를 해결하기 위하여, 본 논문에서는 4상 인터리브드 SEPIC 컨버터를 중심으로 한 고효율 방전 시스템을 설계하였다. 먼저, 낮은 충전상태（SOC 〈 10%）에서의 전기화학적 분극 특성을 분석하고, 히스테리시스 효과를 포함하는 2차 Thevenin 동적 등가회로 모델을 구축하였다. 또한 다항식 피팅（Polynomial fitting）을 이용하여 방전 심도에 따른 옴 저항 및 분극 파라미터의 비선형 드리프트 거동을 정확하게 모델링하였으며, 이를 바탕으로 심방전 후반 단계에서 제어 대상 전달함수 극점의 이동 특성을 규명하여 제어기 설계를 위한 고충실도 모델 기반을 제공하였다. 넓은 이득 운전 범위에서 기존 고정 파라미터 PID 제어기의 안정성 여유가 제한되는 문제를 해결하기 위하여, 구간별 적응형 PID와 입력전압 및 부하전류 피드포워드 보상을 결합한 복합 제어 전략을 제안하였다. 방전 과정에 따라 제어 파라미터를 동적으로 스케줄링함으로써 입력전압 강하로 인해 발생하는 폐루프 불일치를 효과적으로 억제하였다. 또한 특이 섭동 이론（Singular Perturbation Theory）을 이용하여 다중 시간척도 모델링을 수행하였으며, 고속 및 저속 서브시스템 간의 분리 안정성과 구간 전환 과정에서의 과도 응답의 평활성을 이론적으로 입증하였다. 다상 전류 균등 분배를 위해 향상된 평균 전류 균등화 기법을 제안하였으며, MATLAB Function 블록을 이용하여 하위 제어 알고리즘과 상태기계（State Machine） 전환 로직을 구현함으로써 상 탈락（Phase Shedding） 발생 시 위상 이동각의 동적 재구성과 상전류의 원활한 전환을 보장하였다. 심방전 말기의 극한 운전 조건을 고려하여 전류 제한, 상 탈락 운전 및 적응형 차단 보호를 통합한 내고장（Fault-Tolerant） 메커니즘을 설계하였으며, 이를 통해 차단전압 부근에서 “소프트 랜딩（Soft Landing）”을 구현하였다. 마지막으로 MATLAB/Simulink 플랫폼 기반의 전 운전 조건 통합 공동 시뮬레이션 모델을 구축하였다. 시뮬레이션 결과는 2.5 kW 출력 조건에서 전류 리플이 효과적으로 상쇄되었으며, 내부저항의 급격한 증가와 외란 조건에서도 우수한 강인성과 높은 정상상태 추종 성능을 나타냄을 확인하였다. 본 연구는 사용 후 구동용 배터리의 안전한 심방전 재활용을 위한 핵심 전력전자 변환 기술 경로를 제시한다.

목차 (Table of Contents)

• Abstract
• Chapter 1 Background and Engineering Significance of the Investigation 1
• 1.1 Deep Recycling Imperatives Driven by the Retiring Traction Battery Wave 1
• 1.2 The Central Role of Deep Discharge in Securing Battery Recycling and Dismantling Safety 4
• 1.3 Technical Challenges Posed to Power Electronic Converters by High-Power Battery Discharge Regimes 7
• 1.4 Key Bottlenecks in Deep Discharge Systems and the Motivation for This Research 11
• Chapter 2 Deep Discharge Characterization of Spent Power Batteries and Mechanism Analysis of the SEPIC Converter 16
• 2.1 State of the Art in Deep Discharge Modeling of Spent Power Batteries 16
• 2.1.1 Nonlinear Degradation Mechanisms Governing Internal Resistance and Open-Circuit Voltage 16
• 2.1.2 Surge in Internal Resistance Near the End of Deep Discharge: Physical Origins 18
• 2.1.3 Evolution Patterns of the Abrupt Terminal Voltage Drop 20
• 2.1.4 Limitations Inherent in Conventional Constant-Parameter Battery Models 23
• 2.1.5 Progress Toward Variable-Parameter and Time-Varying Nonlinear Battery Representations 25
• 2.1.6 How Internal Resistance Variations Erode the Stability Margin of Closed-Loop Systems 28
• 2.1.7 Performance Bottlenecks of Traditional Control Strategies Across a Wide Input Voltage Range 31
• 2.2 An Overview of Multiphase Interleaved DC–DC Converter Topology Development 35
• 2.2.1 Drawbacks of Conventional Buck–Boost Topologies Under Wide Input Conditions 36
• 2.2.1.1 Electrical Stress on Power Devices Caused by Large Current Fluctuations 36
• 2.2.1.2 The Theoretical Trade-Off Between Single-Inductor Volume and Power Density 38
• 2.2.2 Structural Advantages of Fusing the SEPIC Topology with Multiphase Interleaving 41
• 2.2.2.1 Ripple Cancellation Mechanism in Input and Output Currents Through Phase Interleaving 41
• 2.2.2.2 Theoretical Enhancement of Current Stress Sharing and System Efficiency via Paralleling 43
• 2.2.3 Evolutionary Logic from Basic Choppers to Buck–Boost Composite Topologies 46
• 2.2.3.1 Lack of Flexibility in Unidirectional Buck/Boost Converters for Battery Discharge Voltage Matching 46
• 2.2.3.2 Comparison and Shortcomings of Buck–Boost and Ćuk Converters 48
• 2.2.4 Distinct Advantages of the SEPIC Converter in Deep Discharge Scenarios 51
• 2.2.4.1 Operational Traits: In-Phase Voltage Output and Wide Gain Span 51
• 2.2.4.2 Suppression of Magnetic Coupling Interference via the Intermediate Capacitor Energy Storage 52
• 2.2.5 Emerging Trends in Four-Phase Interleaving and Higher-Order Complex Topologies 55
• 2.2.5.1 Nonlinear Benefit Analysis of Ripple Cancellation Ratio with an Increased Phase Count 55
• 2.2.5.2 Evaluation of Driving Timing Complexity and Computational Cost in Multiphase Systems 56
• 2.3 Advances in Complex Closed-Loop Control Algorithms for Converters 59
• 2.3.1 Mismatch Issues Confronting Conventional PID Control in Wide-Range Variable-Parameter Plants 59
• 2.3.1.1 Stability Boundary Constraints Governed by Small-Signal Linearization Models 60
• 2.3.1.2 Performance Degradation of Fixed-Parameter Controllers in Time-Varying Systems 61
• 2.3.2 Current Status of Feedforward Compensation Control 62
• 2.3.2.1 Fast Rejection Mechanism Targeting Input Voltage Disturbances 62
• 2.3.2.2 Topological Evolution of Combined Feedforward and Feedback Control Structures 63
• 2.3.3 Application of Adaptive Control Algorithms to Variable-Parameter Plants 64
• 2.3.3.1 Parameter Switching and Self-Tuning Control Theory 64
• 2.3.3.2 Gain Self-Scheduling Strategies Tailored to Battery V–Q Curve Characteristics 66
• 2.3.4 Current Balancing Strategies for Multiphase Paralleled Systems 67
• 2.3.4.1 Contrasting Active and Passive Current Sharing Technical Paths 67
• 2.3.4.2 Decoupling Design Challenges Between the Current-Sharing Loop and the Voltage/Current Dual-Loop 68
• 2.4 Probing Internal Polarization Mechanisms and Discharge Behavior of Aged Power Batteries 71
• 2.4.1 Electrochemical Polarization Phenomena in the Deep Discharge Region (SOC < 10%) 71
• 2.4.1.1 Dynamic Features of Ohmic Polarization 71
• 2.4.1.2 Mathematical Formulation of Concentration Polarization 73
• 2.4.1.3 Activation Energy Constraint in Activation Polarization 75
• 2.4.2 Terminal Voltage Plunge Characteristics at Low State of Charge 76
• 2.4.2.1 Nonlinear Zonal Decomposition of the V–Q Curve 76
• 2.4.2.2 Boundary Definition of the Cut-Off Voltage and Its Theoretical Hazards 79
• 2.4.3 Variation of Spent Battery Internal Impedance with Depth of Discharge (DOD) 82
• 2.4.3.1 Logic Behind the Dynamic Evolution of Internal Resistance During Discharge 82
• 2.4.3.2 Time-Constant Simulation Analysis of Polarization Capacitance and Resistance 84
• 2.4.4 Coupled Modeling of Environmental Factors and Aging Degree on Discharge Characteristics 85
• 2.4.4.1 Describing the Superimposed Effect of Cycle Life (SOH) on Polarization Intensity 86
• 2.4.4.2 Simulating Electrochemical Activity Fluctuations Under Temperature Perturbations 87
• 2.4.5 Mechanisms by Which Depth of Discharge Restricts Terminal Voltage and Output Power Capability 88
• 2.4.5.1 Theoretical Influence of Time-Varying Load Behavior on Converter Small-Signal Stability 89
• 2.4.5.2 Assessing Voltage Support Capability Under High-Rate Discharge 91
• 2.5 Battery Equivalent Circuit Modeling Based on Electrochemical Behavior in This System 93
• 2.5.1 Construction of a Second-Order Thevenin Model Incorporating Hysteresis 93
• 2.5.1.1 Topological Configuration and Physical Interpretation of the Second-Order Thevenin Model 93
• 2.5.1.2 Introduction and Parameter Definition of the Dual RC (Dual-Polarization) Network 109
• 2.5.1.3 Matrix-Based State-Space Description of the System Equations 112
• 2.5.2 Mathematical Integration of Battery Hysteresis Effects 114
• 2.5.2.1 Mechanism Analysis Behind Hysteresis Voltage "U" _"h" Generation 114
• 2.5.2.2 Comparison of the Zero-State Hysteresis Model with the Dynamic Hysteresis Model 117
• 2.6 Theoretical Design and Analysis of an Adaptive Four-Phase Interleaved Parallel SEPIC Converter 122
• 2.6.1 Modal Analysis of a Single-Phase SEPIC Under Ideal Conditions 122
• 2.6.1.1 Functional Partitioning of Core Energy Storage Elements 122
• 2.6.1.2 Derivation of Circuit Modal Change Equations 126
• 2.6.2 Steady-State Characteristics and Voltage Gain Formula Derivation 129
• 2.6.2.1 Application of the Inductor Volt-Second Balance Principle 129
• 2.6.2.2 Application of the Capacitor Charge Balance Principle 134
• 2.6.2.3 Contrasting Ideal Gain and Non-Ideal Gain (Including Losses) 136
• 2.6.3 Summary of Voltage and Current Waveform Features at Crucial Nodes 140
• 2.6.3.1 Mathematical Voltage Stress Analysis for Switch and Diode 141
• 2.6.3.2 Theoretical Discussion on Input/Output Current Continuity 144
• 2.6.4 Four-Phase 90° Phase-Shifted Driving and Ripple Cancellation Mechanism 146
• 2.6.4.1 Physical Proof of Total Input Current Ripple Nullification 148
• 2.6.4.2 Time-Domain Overlap Analysis of Individual Phase Inductor Currents 149
• 2.6.4.3 Mathematical Explanation of the Ripple Frequency Multiplication Effect 150
• 2.6.5 Derivation and Scrutiny of the Ripple Suppression Coefficient K(D) 151
• 2.6.5.1 Mathematical Definition of the Ripple Suppression Coefficient 151
• 2.6.5.2 Piecewise Function Expressions Across Different Duty CycleRanges 152
• 2.6.5.3 Ripple Performance Evaluation Throughout the Deep Discharge Process 154
• 2.6.5.4 Logic Construction and Software Implementation of the Interleaved PWM Signals 155
• 2.6.6 State-Space Averaged Modeling and System Dynamic Analysis 156
• 2.6.6.1 Derivation of State Equations in Continuous Conduction Mode (CCM) 157
• 2.6.6.2 Tracing the Locus of System Pole Migration Under a Wide Duty Cycle Range 159
• 2.6.7 Theoretical Optimization of Dynamic Response Through Magnetic Component Parameter Selection 160
• 2.6.7.1 Criteria for Selecting Equivalent Inductance Values 161
• 2.6.7.2 Weighing Dynamic Response Speed Against Ripple Suppression 161
• 2.6.8 Simulation Significance of Phase-Shift Control for Prolonging Spent Battery Life 163
• 2.6.8.1 Modeling Reduction of High-Frequency Current Stress at the Battery Terminal 164
• 2.6.8.2 Theoretical Discussion on Mitigating Electrochemical Polarization Buildup 165
• Chapter 3 Simulation Model Design 167
• 3.1 Equivalent Research on High-Power Battery Models Based on Singular Perturbation Theory 167
• 3.1.1 Limitations of Traditional High-Order Electrochemical Battery Simulation Models 167
• 3.1.1.1 Issues of Restricted Simulation Step Size and High Computational Cost Caused by Stiff Equations 168
• 3.1.1.2 Coupling Bottlenecks of Complex State-Space Descriptions in Converter Transient Simulation 170
• 3.1.1.3 Problems of Excessive Data Storage and Memory Resource Consumption 171
• 3.1.2 Application of Singular Perturbation Theory (SPT) in Battery Model Reduction 171
• 3.1.2.1 Core Mathematical Foundations and Slow-Fast Time-Scale Separation Principles of SPT 171
• 3.1.2.2 Selection of Perturbation Parameters and Singularity Criteria for Battery Model Order Reduction 173
• 3.1.2.3 Reduced-Order Mapping of Slow Subsystems (Energy Evolution) and Fast Subsystems (Converter Switching) Based on Time-Scale Separation 176
• 3.1.3 Physical Mapping and Structural Implementation of Equivalent Battery Models 177
• 3.1.3.1 Battery Reduced-Order Representation Logic Under Singular Perturbation Models 177
• 3.1.3.2 Non-linear Equivalent Circuit Parameter Identification Considering Dynamic Internal Resistance Variations 178
• 3.1.3.3 Implementation of Reduced-Order Models in Simulink Environment and Comparative Analysis of Computational Efficiency 179
• 3.1.4 Equivalent Error Analysis and Model Effectiveness Verification 182
• 3.1.4.1 Analysis of the Impact of Perturbation Truncation Error on Converter Output Ripple Accuracy 182
• 3.1.4.2 Steady-State Output Characteristic Verification of Equivalent Models at Different SOC Stages 183
• 3.1.4.3 Model Fidelity and Computational Performance Evaluation Under High-Power Dynamic Response 184
• 3.2 Adaptive Dual-Loop Control Strategy Design Oriented to Operating Condition Changes 186
• 3.2.1 Dual-Loop Control Architecture for Four-Phase Interleaved SEPIC Converters 186
• 3.2.1.1 Transfer Function Modeling and Loop Response Characteristic Analysis of the Voltage Outer Loop 187
• 3.2.1.2 Rapid Current Tracking Capability and Stability Constraints of the Current Inner Loop 189
• 3.2.1.3 Dynamic Decoupling Cooperative Control Logic Design Under Dual-Loop Architecture 191
• 3.2.2 Target Voltage Adaptive Regulation Strategy Driven by Battery Voltage 192
• 3.2.2.1 Mathematical Modeling of Battery Terminal Voltage Evolution Characteristics During Deep Discharge 192
• 3.2.2.2 Target Voltage Correction Interval Partitioning Based on Battery State of Charge (SOC) and Terminal Voltage Mapping 194
• 3.2.2.3 Target Voltage Tracking Logic and Non-linear Adaptive Reference Trajectory Design 196
• 3.2.2.4 Advantages of Adaptive Tracking Strategies in Improving System Stability and Control Accuracy 197
• 3.2.3 PID Parameter Online Self-Scheduling Algorithm Based on Operating Condition Segmentation 199
• 3.2.3.1 Mechanism of PID Gain Self-Correction Logic Driven by Discrete Target Voltages 199
• 3.2.3.2 Optimal PID Parameter Design Method Under Continuous Conduction Mode (CCM) 200
• 3.2.3.3 Robust PID Parameter Control Design Under Discontinuous Conduction Mode (DCM) 201
• 3.2.3.4 Coupling Mapping Relationships Among Battery Voltage, Converter Operating Modes, and PID Gains 202
• 3.2.3.5 Impact of Discrete Sampling Frequency on Transient Shocks During Parameter Switching and Their Suppression 203
• 3.3 Enhancement of System Disturbance Rejection Performance and Multi-Phase Control Optimization 205
• 3.3.1 Control Design Based on Power Feed-Forward 205
• 3.3.1.1 Power Balance Principle and Predictive Estimation of System Duty Cycle 205
• 3.3.1.2 Improvement of System Response Speed Through the Synergistic Effect of Feedback Regulation and Feed-Forward Compensation 206
• 3.3.2 Current Sharing Control Algorithm for Four-Phase Interleaved SEPIC 207
• 3.3.2.1 Physical Roots and Theoretical Basis of Current Mismatch in Each Phase Branch 207
• 3.3.2.2 Modeling and Implementation of Current Sharing Strategies Under Master-Slave Control Mode 208
• 3.3.2.3 Quantitative Evaluation of the Correlation Between Current Sharing Accuracy and Converter Output Ripple 208
• 3.3.2.4 Decoupling Coordination Mechanism Between Feed-Forward Compensation and Current Sharing Control Algorithms 209
• 3.3.3 Phase-Shedding Control and Control Mode Algorithm Design Based on Load Dynamics 210
• 3.3.3.1 Principles of Multi-Phase Interleaved Operating Mode Switching Under Different Load Demands 211
• 3.3.3.2 Comparison of Output Voltage Ripple Smoothness Under 4-Phase/2-Phase/1-Phase Operating Modes 211
• 3.3.3.3 Inductor Current Surge Suppression and Seamless Switching Implementation Strategy During Phase-Shedding 212
• 3.3.3.4 Optimization of System Conversion Efficiency Under Light Load Conditions via Phase-Shedding Control 213
• 3.3.4 System Control Mode Switching Management 214
• 3.3.4.1 State Transition Logic Model 214
• 3.3.4.2 Mode Switching Control Architecture 217
• 3.4 Construction of Four-Phase Interleaved SEPIC System Simulation Platform and Condition Verification 222
• 3.4.1 Integrated Modeling Design of Control System and Main Circuit 223
• 3.4.1.1 Modular Simulation Platform Architecture: Main Circuit and Control Logic Topology Construction Based on Simulink 223
• 3.4.1.2 Physical Modeling Implementation of Four-Phase Interleaved Branches and Their Coupled Inductors 226
• 3.4.1.3 Modular Encapsulation of Adaptive Control Logic: Integration of PID Control, Feed-Forward Compensation, and Phase-Shedding Modules 229
• 3.4.2 Parameter Setting and Operating Environment Configuration for the Simulation System 229
• 3.4.2.1 Simulation Step Size Selection Strategy: A Trade-off Scheme Between Computational Accuracy and Simulation Speed 230
• 3.4.2.2 Initial Settings for Key Circuit Parameters 233
• Chapter 4 Simulation Results and Data Analysis 236
• 4.1 Independent Simulation Waveforms and Data Analysis for Rated Normal Operating Condition (50V Target) 236
• 4.1.1 Time-Domain Waveform Analysis of Battery Model External Characteristics Under 50V Independent Condition 236
• 4.1.1.1 Analysis of Battery Terminal Voltage Drop and Recovery Waveforms During 50V Independent Startup Transient 236
• 4.1.1.2 Data on Battery Terminal Voltage Ripple and DC Offset Under 50V Steady-State Operation 240
• 4.1.2 Topological State Analysis of Four-Phase Interleaved SEPIC Converter Under 50V Independent Condition 242
• 4.1.2.1 Quantization of Steady-State Ripple Rate and DC Accuracy for Rated 50V Output Voltage and Current 242
• 4.1.2.2 Analysis of Interleaved Phase-Shift Waveforms and Current Sharing Error Data of Four-Phase Energy Storage Inductors 245
• 4.1.2.3 Interpretation of Steady-State Distribution Waveforms of Multi-Phase Adaptive Drive Duty Cycles Corresponding to 50V Output 246
• 4.1.3 Quality Assessment of Dual-Loop Adaptive Control Under 50V Independent Condition 249
• 4.1.3.1 Analysis of Tracking Error Time-Domain Convergence Speed and Steady-State Error During 50V Independent Startup 249
• 4.1.3.2 Steady-State Evolution Trajectory of Key Adaptive PID Controller Gain Parameters at 50V 250
• 4.1.3.3 Quantization of Time-Domain Metrics Including Overshoot and Settling Time for 50V Startup Full Dynamic Curves 251
• 4.2 Independent Simulation Waveforms and Data Analysis for Fine-Tuning Operating Condition (45V Target) 254
• 4.2.1 Simulation Waveform Interpretation of 45V Operating Condition Physics and Battery External Characteristics 255
• 4.2.1.1 Design Background Data and Physical Correlation Analysis of Battery State Under 45V Independent Condition 255
• 4.2.1.2 Characteristic Analysis of Transient Battery Terminal Voltage Dip Waveforms During 45V Independent Startup 255
• 4.2.1.3 Calculation of Time-Domain Ripple and Mean Data for Battery Output Current Under 45V Steady-State Operation 257
• 4.2.2 Analysis of Internal Energy Conversion State of Converter Topology Under 45V Condition 258
• 4.2.2.1 Static Accuracy and DC Component Extraction of 45V Independent Output Voltage and Current 258
• 4.2.2.2 Interleaved Waveforms and Current Sharing Standard Deviation of Four-Phase Energy Storage Inductor Currents at 45V Steady-State Point 260
• 4.2.2.3 Time-Domain Waveform Performance of Each Phase’s Adaptive Drive Duty Cycle Corresponding to 45V Output 262
• 4.2.2.4 Phase-Shift Cancellation Effect of Total Output Current Ripple of the Converter Under 45V Output 264
• 4.2.3 Quality of Adaptive Control and Quantization of Time-Domain Metrics Under 45V Independent Condition 265
• 4.2.3.1 Analysis of Control System Tracking Error Convergence Speed During 45V Independent Startup 266
• 4.2.3.2 Presentation of Steady-State Convergence Values of Adaptive PID Control Gains Corresponding to 45V Target 267
• 4.2.3.3 Measurement of Transient Overshoot Coefficient and Settling Time During System 45V Independent Startup 268
• 4.3 Independent Simulation Waveforms and Data Analysis for Medium-Voltage Operating Condition (25V /15V Target) 270
• 4.3.1 Simulation Waveform Interpretation of Medium-Voltage Operating Condition Physics and Battery External Characteristics 270
• 4.3.1.1 Design Background Data of Medium-Voltage Condition and Correlation Analysis with Power Battery Deep Discharge Behavior 270
• 4.3.1.2 Interpretation of Time-Domain Evolution Curves of Battery Terminal Voltage During Independent Startup 271
• 4.3.1.3 Waveform Characteristics of Battery Output Current Under Steady-State Operation 272
• 4.3.2 Analysis of Internal Energy Conversion State of Converter Topology Under 25V Condition 273
• 4.3.2.1 Interpretation of AC/DC Transient Response Curves of 25V Independent Output Voltage and Current 274
• 4.3.2.2 Distribution Characteristics of Four-Phase Interleaved Duty Cycles at 25V Operating Point Under Wide-Range Regulation 275
• 4.3.3 Quality Assessment of Adaptive Control System Under 25V Independent Condition 277
• 4.3.3.1 Quantitative Assessment of Smoothness (Non-Oscillatory and Non-Overshoot) of 25V Independent Startup Response Curves 277
• 4.3.3.2 Presentation of Non-linear Convergence Stable Values of Adaptive PID Parameters at 25V Independent Operating Point 278
• 4.3.3.3 Data Analysis of Dynamic Regulation Range and Static Accuracy of 25V Steady-State Tracking Error 278
• 4.3.4 Deconstruction of Converter Port Power Quality Simulation Data Under 15V Condition 279
• 4.3.4.1 Calculation and Comparison of Time-Domain Ripple Rates of Output Voltage and Current Under 15V Low-Voltage Steady-State 280
• 4.3.4.2 Time-Domain Waveform Analysis of Discontinuous and Continuous States of Four-Phase Energy Storage Inductor Currents During Low Voltage Output 282
• 4.3.4.3 Verification of Non-Saturation State of Time-Domain Duty Cycle of Each Converter Phase Under Extremely Low Output Levels 283
• 4.3.4.4 Analysis of Total Output Current Ripple Cancellation Mechanism of Four-Phase Interleaved Topology at 15V Steady-State Point 285
• 4.3.5 Quality Assessment of Adaptive Control System Under Medium-Voltage Independent Condition 286
• 4.3.5.1 Time-Domain Measurement Data of System Voltage Settling Time During Entire Medium-Voltage Independent Startup Process 286
• 4.3.5.2 Presentation of Static Mapping Data of Adaptive PID Control Gains Under Medium-Voltage Condition 288
• 4.3.5.3 Quantization of Comprehensive Tracking Steady-State Error and Stability of the System During Medium-Voltage Steady-State Operation 290
• 4.4 Independent Simulation Waveforms and Data Analysis for Extreme Low-Voltage Operating Condition (5V Target) 292
• 4.4.1 Simulation Waveform Interpretation of 5V Extreme Operating Condition Physics and Battery External Characteristics 292
• 4.4.1.1 Design Background Data of 5V Extreme Low-Voltage Condition and Correlation Analysis with Control Dead-Zone Boundary Conditions 292
• 4.4.1.2 Interpretation of Transient Decay Waveform Laws of Battery Terminal Voltage During 5V Extreme Independent Startup 294
• 4.4.1.3 Time-Domain Component Extraction of Voltage Drop Across Equivalent Ohmic Internal Resistance Within Battery at 5V Operating Point 294
• 4.4.2 Analysis of Converter Topological Behavior Simulation Waveforms Under 5V Extreme Condition 296
• 4.4.2.1 Quantized Measurement of Ripple Coefficient Waveforms of Output Voltage and Current Under 5V Extreme Steady-State 296
• 4.4.2.2 Characterization of Time-Domain Pulse Width Distortion of Four-Phase Interleaved Chopper Circuit Under Extremely Low Duty Cycles 298
• 4.4.2.3 Data on Adaptive Correction of Severe Imbalance in Multi-Phase Inductor Currents Under Extreme Conditions 300
• 4.4.3 Data Deconstruction of Adaptive Control Quality Under Low voltage Extreme Condition 301
• 4.4.3.1 Presentation of Saturation and Regulation Trajectory Curves of Adaptive PID Parameters Under Low voltage Extreme Condition 301
• 4.4.3.2 Quantitative Assessment of Convergence Speed and Oscillation Frequency of Low voltage Independent Startup Full Dynamic Response 302
• 4.4.3.3 Statistics of Residual Steady-State Error Rate of Adaptive Control System Under Low voltage Extreme Steady-State Operation 304
• Chapter 5 Analysis of Over-Discharge Condition and System Multi-Mode Transient Response 309
• 5.1 Time-Domain Waveform Analysis of Battery Multi-Physical Field Coupling State Under Over-Discharge Conditions 309
• 5.1.1 Time-Domain Waveform Interpretation of Battery Port Electrical Characteristics (Voltage and Current) 309
• 5.1.1.1 Time-Domain Waveforms of Continuous Attenuation Characteristics of Battery Output Current Under Deep Over-Discharge Dynamics 309
• 5.1.1.2 Data Curve Analysis of Non-linear Accelerated Drop in Battery Terminal Voltage at the Over-Discharge Critical Point 312
• 5.1.2 Analysis of Evolution Trajectory Characteristics of Battery Internal State (SoC and Temperature) 315
• 5.1.2.1 Steady-State Depletion Curve of Battery State of Charge (SoC) Throughout the Over-Discharge Process 315
• 5.1.2.2 Data on Battery Electro-Thermal Coupling Temperature Rise Curves Caused by Sustained High-Current Discharge 317
• 5.1.3 Analysis of the Impact of Intensified Battery Polarization State on Control System Input Characteristics 319
• 5.1.3.1 Presentation of Adaptive Target Value Dynamic Mapping Waveforms Triggered by Battery Terminal Voltage Decline 321
• 5.1.3.2 Statistical Distribution of System Tracking Errors in the Time-Domain Caused by Increased Polarization Resistance During the Late Over-Discharge Phase 322
• 5.2 Transient Waveforms and Data Analysis of Multi-Mode Switching Under Over-Discharge Safety Mechanisms 325
• 5.2.1 Deconstruction of Time-Domain Response Waveforms for Adaptive Control Mode Self-Switching 325
• 5.2.1.1 Time-Domain Transient Waveforms at the Instant of Control Mode Switching When Triggering Over-Discharge Voltage Thresholds 325
• 5.2.1.2 Quantization of Output Voltage and Current Pulse Peaks During the Dynamic Transition Period of Control Mode Switching 326
• 5.2.1.3 Comparison of Convergence Trajectories of Adaptive Dual-Loop PID Parameters Before and After Control Mode Switching 327
• 5.2.2 Analysis of Sequential Switching Behavior During Discharge Protection Mechanism Activation 328
• 5.2.2.1 Interpretation of Sequential Characteristics of the Transition from Normal Discharge Mode to Safety Current Limiting/Cut-off Discharge Mode 328
• 5.2.2.2 Quantitative Measurement of Activation Latency and Transient Recovery Time of Discharge Mode Switching Mechanisms in the Time-Domain 329
• 5.3 Analysis of Converter Output Characteristics and Multi-Phase Modulation Waveforms Throughout the Over-Discharge Process 330
• 5.3.1 Time-Domain Interpretation of Converter Port Power Quality (Output Voltage and Current) 330
• 5.3.1.1 Data Analysis of Converter Output Voltage DC Drop Curves Accompanying Battery Over-Discharge Evolution 330
• 5.3.1.2 Transient Overshoot and Static Ripple Rate of Load-Side Output Current Under Multi-Mode Switching Shocks 332
• 5.3.1.3 Comprehensive Evaluation of Power Quality Metrics for the SEPIC Converter Throughout the Over-Discharge Process 334
• 5.3.2 Deconstruction of Internal Adaptive Modulation Parameter Waveforms for Four-Phase Interleaved Topology 335
• 5.3.2.1 Time-Domain Reconstruction Waveforms of Multi-Phase Adaptive Drive Duty Cycles Corresponding to the Battery Voltage Sliding Process 335
• 5.3.2.2 Characteristic Waveforms of Converter Clipping at the Edge of Over-Discharge Under Asymmetric Wide-Duty-Cycle Modulation 336
• 5.3.2.3 Analysis of Dynamic Current Sharing Standard Deviation of Four-Phase Energy Storage Inductor Currents During Discharge Mode Transitions 337
• Chapter 6 Conclusions and Outlook 341
• 6.1 Summary of the Thesis 341
• 6.2 Summary of Innovations 344
• 6.3 Limitations and Future Prospects 346
• 6.4 Future Research Plans 349
• 6.5 Acknowledgments 354
• List of References 357