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      반도체 패키징용 Bond pad와 Bonding wire의 부식거동에 미치는 황산농도의 영향

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      https://www.riss.kr/link?id=T17511178

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      다국어 초록 (Multilingual Abstract) kakao i 다국어 번역

      Wire bonding remains widely used in semiconductor packaging, but combined degradation can occur at bond pad-wire interfaces during use or storage due to humidity, acidity, and ionic contamination, leading to galvanic corrosion, oxidation, and sulfidation. In particular, Al pad-wire and ENIG Au pad-wire structures contain Al, Ni, Au, Cu, and intermetallic compounds (IMCs), so localized galvanic corrosion can be concentrated at specific regions in sulfuric acid-containing sulfate environments. In this thesis, packaging structures composed of sputtered Al pads and ENIG Au pads on 4-inch Si wafers, combined with Au, Cu, Cu-Pd alloy (Cu1Pd), and Pd-coated Cu (PCC) wires, were systematically investigated in de-aerated 1 % Na₂SO₄ solutions with varying H₂SO₄ concentrations (x = 0, 0.1, 1, 10 %). Individual polarization and electrochemical galvanic tests were conducted to obtain the corrosion potential (Ecorr), corrosion current density (icorr), galvanic potential/current density, and corrosion rate estimated from the total charge. In addition, Temperature-Humidity Tests (85 °C / 85 % RH) were performed under 1 % Na₂SO₄ + 0 % or 1 % H₂SO₄ conditions using FR-4 PCB unit specimens in which a 1st ball bond was formed on an Al pad and a 2nd stitch bond on an Au pad with Au, Cu, Cu1Pd, or PCC wires, and the surface morphology and elemental distribution around ball bonds, stitch bonds, and wires were examined using a 3D optical microscope and FE-SEM/EDS. By correlating electrochemical results with THT observations, the effects of sulfuric acid concentration and pad-wire material combinations on galvanic corrosion behavior, the difference in corrosion resistance between Au and Cu wires, and the effects and limitations of Pd alloying/coating in Cu-based wires were elucidated.
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      Wire bonding remains widely used in semiconductor packaging, but combined degradation can occur at bond pad-wire interfaces during use or storage due to humidity, acidity, and ionic contamination, leading to galvanic corrosion, oxidation, and sulfidat...

      Wire bonding remains widely used in semiconductor packaging, but combined degradation can occur at bond pad-wire interfaces during use or storage due to humidity, acidity, and ionic contamination, leading to galvanic corrosion, oxidation, and sulfidation. In particular, Al pad-wire and ENIG Au pad-wire structures contain Al, Ni, Au, Cu, and intermetallic compounds (IMCs), so localized galvanic corrosion can be concentrated at specific regions in sulfuric acid-containing sulfate environments. In this thesis, packaging structures composed of sputtered Al pads and ENIG Au pads on 4-inch Si wafers, combined with Au, Cu, Cu-Pd alloy (Cu1Pd), and Pd-coated Cu (PCC) wires, were systematically investigated in de-aerated 1 % Na₂SO₄ solutions with varying H₂SO₄ concentrations (x = 0, 0.1, 1, 10 %). Individual polarization and electrochemical galvanic tests were conducted to obtain the corrosion potential (Ecorr), corrosion current density (icorr), galvanic potential/current density, and corrosion rate estimated from the total charge. In addition, Temperature-Humidity Tests (85 °C / 85 % RH) were performed under 1 % Na₂SO₄ + 0 % or 1 % H₂SO₄ conditions using FR-4 PCB unit specimens in which a 1st ball bond was formed on an Al pad and a 2nd stitch bond on an Au pad with Au, Cu, Cu1Pd, or PCC wires, and the surface morphology and elemental distribution around ball bonds, stitch bonds, and wires were examined using a 3D optical microscope and FE-SEM/EDS. By correlating electrochemical results with THT observations, the effects of sulfuric acid concentration and pad-wire material combinations on galvanic corrosion behavior, the difference in corrosion resistance between Au and Cu wires, and the effects and limitations of Pd alloying/coating in Cu-based wires were elucidated.

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      목차 (Table of Contents)

      • 제1장 서론 1
      • 제2장 이론적 배경 4
      • 2.1 반도체 패키징 4
      • 2.1.1 반도체 패키징 공정 4
      • 2.1.2 패키징의 전기적 연결 방식 7
      • 제1장 서론 1
      • 제2장 이론적 배경 4
      • 2.1 반도체 패키징 4
      • 2.1.1 반도체 패키징 공정 4
      • 2.1.2 패키징의 전기적 연결 방식 7
      • 2.1.2.1 Flip Chip Bonding 7
      • 2.1.2.2 Through Silicon Via(TSV) 7
      • 2.1.2.3 Hybrid Bonding 8
      • 2.1.2.4 Wire Bonding 8
      • 2.2 전기적 연결시 발생하는 부식 사례 12
      • 2.2.1 Bond pad 부식 및 pad lifting 12
      • 2.2.2 Bonding wire 부식 및 단선 12
      • 2.2.3 Pad-wire 계면에서의 갈바닉 부식 14
      • 제3장 연구 방법 16
      • 3.1 시험편 16
      • 3.1.1 Al pad 16
      • 3.1.2 Bonding wire 16
      • 3.1.3 PCB Unit 17
      • 3.2 분극 시험 17
      • 3.3 갈바닉 부식 시험 18
      • 3.4 항온 항습 테스트 18
      • 3.5 표면 관찰 19
      • 제4장 연구결과 및 고찰 22
      • 4.1 Au wire bond부와 Cu wire bond부의 부식거동 비교 22
      • 4.1.1 단독 시편의 전기화학적 부식 거동 분석 22
      • 4.1.2 갈바닉 쌍의 전기화학적 부식 거동 분석 27
      • 4.1.3 항온항습시험을 통한 화학적 부식 거동 분석 32
      • 4.2 Cu wire bond부의 부식저항성 향상을 위한 Pd 합금화 및 Pd 코팅의 영향 44
      • 4.2.1 단독 시편의 전기화학적 부식 거동 분석 44
      • 4.2.2 갈바닉 쌍의 전기화학적 부식 거동 분석 50
      • 4.2.3 항온항습시험을 통한 화학적 부식 거동 분석 56
      • 제5장 결론 73
      • 5.1 Au wire bond부와 Cu wire bond부의 부식거동 비교 73
      • 5.2 Cu wire bond부의 부식저항성 향상을 위한 Pd 합금화 및 Pd 코팅의 영향 73
      • 참고 문헌 75
      • Abstract 82
      • 감사의 글 83
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