In recent years, graph applications demand fast accesses to massive data. Graph-based Approximate Nearest Neighbor Search (ANNS) is now a key operation in production search engines and Retrieval-Augmented Generation (RAG) systems. Sparse Matrix-Matrix...
In recent years, graph applications demand fast accesses to massive data. Graph-based Approximate Nearest Neighbor Search (ANNS) is now a key operation in production search engines and Retrieval-Augmented Generation (RAG) systems. Sparse Matrix-Matrix Multiplication (SpMM) and Sampled Dense-Dense Matrix Multiplication (SDDMM) are fundamental kernels in various applications, such as Graph Neural Network (GNN). These workloads combine sparse graph traversal with accesses to large embedding matrices, which produce irregular, data-dependent accesses of high-dimensional vectors with little spatial or temporal locality and poor predictability. As a result, multi-level caches and conventional prefetchers are ineffective, and conventional systems become strongly memory-latency bound. This thesis addresses these memory latency issues shared by emerging graph applications.
This dissertation develops two techniques that optimize memory behavior in distinct scenarios, one in software and one in hardware. On the software side, we introduce a lightweight approximation for graph-based ANNS that exploits a key property of search: only a small subset of high-similarity neighbors materially affects the result. By performing low-cost, direction-aware screening to select only neighbors that are likely relevant, the method reduces unnecessary vector fetches and distance evaluations, thereby cutting memory-latency-dominated work. The technique incurs modest metadata overhead, is index-agnostic, and we validate it across multiple popular graph indices.
On the hardware side, we present VIPER, a prefetcher for SpMM and SDDMM. VIPER leverages software hints about the traversal and indirection structure to guide prefetching, bringing the right slices of high-dimensional vectors into the cache ahead of use. It integrates prefetch throttling to avoid overfetching, and uses L2 cache as a buffer, loading data early so that subsequent L1 misses are served as L2 hits rather off-core accesses, thereby making better use of available memory bandwidth and increasing effective memory-level parallelism. As a result, VIPER remains effective even at high vector dimensionality, where naive prefetchers typically struggle.