Copper interconnects in advanced semiconductor packaging require simultaneous control of void formation, height uniformity, surface planarity, and microstructural stability. In this study, a copper electroplating process was developed that addresses t...
Copper interconnects in advanced semiconductor packaging require simultaneous control of void formation, height uniformity, surface planarity, and microstructural stability. In this study, a copper electroplating process was developed that addresses these requirements through three integrated components, pretreatment of photoresist (PR) patterned wafers for Cu pillar fabrication, high rate Cu pillar electrodeposition using a multi additive electrolyte, and electrodeposition of highly (111) oriented nanotwinned Cu (NT-Cu) suitable for interconnect and bonding applications.
In the first part, the role of pretreatment on PR-patterned wafers was evaluated to enable stable Cu pillar formation. As-received wafers often trapped air inside PR vias and contained residual PR and native oxide at the seed interface, all of which interfered with electrolyte penetration and uniform deposition. To address this, a sequential pretreatment using DI water spray, ethanol rinsing, and citric acid conditioning was applied to improve wetting and surface cleanliness. With this process, Cu pillars were deposited without voids or cracking, and the height variation across the wafer was significantly reduced, confirming that adequate surface conditioning is essential for reliable Cu pillar electrodeposition.
In the second part, high-rate Cu pillar plating was investigated using a multi- additive electrolyte. When the current density was doubled, conventional SPS with PEG-PPG suppressors generated severe hole defects, and suppressor screening revealed that polymer-based species inherently fail under rapid plating. To overcome this limitation, the suppressors were removed and a new system combining SPS with two levelers, Allyl_A3_Br and JGB, was introduced, which effectively eliminated hole defects and yielded smooth, well-filled pillars. Potential analysis showed that Allyl_A3_Br provides broad suppression, while JGB selectively moderates deposition near the pillar center. By adjusting the rotation speed, an optimal condition of 2000 rpm was identified, producing planar, tilt-free pillars with minimized TIR and surface roughness.
In the third part, the formation of highly (111) oriented NT-Cu was investigated using an electrolyte containing gelatin and ammonium bromide. Without additives, the deposited Cu showed coarse, mixed-orientation grains with no twinning, while gelatin alone promoted some twins but not strong (111) texturing. Introducing a small amount of NH4Br together with gelatin markedly enhanced the (111) reflection and produced dense coherent twins, as confirmed by XRD, FIB-SEM, and EBSD. The combination of 30 ppm gelatin and 5 µM NH4Br yielded the most selective (111) orientation and twin density, whereas higher NH4Br levels diminished the effect. These results indicate that the inorganic additive reinforces the twinning and texturing tendencies initiated by gelatin.
Taken together, these findings show that integrating optimized wafer pretreatment, multi additive high rate electrodeposition, and inorganic additive assisted NT-Cu deposition enables the fabrication of Cu pillars and NT-Cu layers that satisfy the demands of modern wafer level and three dimensional packaging. The proposed process framework offers both practical guidelines and a microstructural design strategy for implementing defect free, planar, and structurally robust Cu interconnects in next generation semiconductor devices.