Design of High-Speed and Low-Power Transceivers for Die-to-Die Chiplet and Memory Interfaces = 다이-투-다이 칩렛 및 메모리 인터페이스용 고속 저전력 트랜시버 설계

국문 초록 (Abstract)

본논문에서는칩렛환경의다이-투-다이인터페이스를위한고속· 저전력· 고
신뢰성트랜시버를구현한두개의칩을기술한다. 첫번째칩은42 Gb/s의고속에서
0.275 pJ/b의에너지효율을달성하는단일종단클럭레퍼런스PAM3 (CR-PAM3)
트랜시버를제안한다. 제안된CR-PAM3 신호방식은포워드된클록을기준전압으
로활용함으로써, 단일종단다이-투-다이인터페이스에서발생하는공급노이즈와
기준전압오프셋에대한내성을제공한다. PAM3의전력소모를최소화하기위해
차등가중데이터드라이버를사용하였으며, 제안된XTC-결합FS 풀러는인접채널
로부터의FEXT를상쇄하면서전압레벨전환을촉진한다. DFE가내장된샘플러는
CML 서머구조를제거하고탭브랜치를샘플러에직접추가함으로써1 UI 이내의
저전력피드백을가능하게한다. 프로토타입칩은28 nm CMOS 공정에서구현되
었다.
두번째칩은56 Gb/s의고속에서0.292 pJ/b의에너지효율을달성하는캐패
시티브구동동시양방향(CD-SBD) 트랜시버를기술한다. 제안된CD-SBD 신호
방식은SBD 구조에서의전력소모와자기간섭(self-interference)을감소시킨다. 하
이브리드구조에서의불일치와PVT 변동을최소화하기위해AC/DC 레플리카회로
및PVT/불일치추적기법을제안하였다. 특히PVT/불일치추적은CDR이활용하는
데이터및엣지샘플정보만을재사용함으로써추가하드웨어없이PVT 강건성을
제공한다. 레인별CDR과QEC/DCC 기능을포함한직교클럭생성기는최소한의전
력및면적오버헤드로충분한클록마진을확보한다. 해당트랜시버는-6.5 dB에서
-11.5 dB까지의채널손실, 0.93–1.2 V의공급전압, 0–80 °C의온도변화환경에서
¡1e-12의BER을유지한다. 프로토타입칩은28 nm CMOS 공정에서구현되었다.

다국어 초록 (Multilingual Abstract)

This paper describes two chips for high data rate, low power, robust transceiver for
die-to-die interface in chiplet. The first chip describes a single-ended clock-referenced
PAM3 (CR-PAM3) transceiver that achieves an energy efficiency of 0.275 pJ/b at a
high data rate of 42 Gb/s. The proposed CR-PAM3 signaling provides tolerance to
supply noise and reference offset in single-endeddie-to-die interfaces by using for-
warded clock as reference voltages. To minimize power consumption for PAM3, a dif-
ferentially weighted data driver is employed. The proposed XTC-combined FS puller
helps voltage level transition while canceling FEXT from adjacent channels. A DFE-
embedded sampler enables low-power feedback within 1 UI by eliminating the CML
summer structure and directly adding a tap branch to the sampler. Prototype chip was
implemented in a 28 nm CMOS technology. The second chip describes a capacitively
driven simultaneous bidirectional (CD-SBD) TRX that achieves an energy efficiency
of 0.292 pJ/b at a high data rate of 56 Gb/s. The proposed CD-SBD signaling re-
duces power and self-interference in SBD. To minimize mismatch and PVT variation
in hybrid, AC/DC replica and PVT/mismatch tracking are proposed. PVT/mismatch
tracking provides PVT robustness without extra hardware, reusing only data and edge
sample information that CDR utilizes. Per-lane CDR and a quadrature generator with
QEC/DCC secure clock margin, with minimal power and area overhead. The TRX
sustains ¡1e-12 BER across -6.5 to -11.5dB loss, 0.93-1.2V supply, and 0-80°C tem-
perature variation. Prototype chip was implemented in a 28 nm CMOS technology.

목차 (Table of Contents)

• 1 Introduction 1
• 2 Backgrounds on Die-to-die Interfaces 3
• 2.1 Short-reach channel in Chiplets 3
• 2.2 Signaling candidate 1: PAM 18
• 2.3 Signaling candidate 2: Capacitive Driving 20
• 2.4 Signaling candidate 3: SBD 21
• 3 A 42 Gb/s/wire Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver 24
• 3.1 Overview 24
• 3.2 Clock-referenced PAM3 signaling 27
• 3.3 Transmitter Design 31
• 3.3.1 Low-Power PAM3 Data Driver 31
• 3.3.2 Amplitude-Modulating Clock Driver 37
• 3.4 Receiver Design 40
• 3.4.1 RX Data Path 40
• 3.4.2 RX Clock Path 43
• 3.5 Foreground Calibration 45
• 3.5.1 Clock Alignment and Per-Lane Deskew Calibration 45
• 3.5.2 Clock Level Calibration 46
• 3.6 CR-PAM3 Noise Tolerance 47
• 3.6.1 Supply Noise Injection 47
• 3.6.2 Noise Rejection with CR-PAM3 49
• 3.7 Measurement Results 52
• 4 A 0.292pJ/b 56Gb/s/wire Capacitively Driven Simultaneous Bidirectional Transceiver with PVT/Mismatch Tracking 59
• 4.1 Overview 59
• 4.2 CD-SBD Signaling 61
• 4.2.1 Channel characteristics of D2D 61
• 4.2.2 Signaling Scheme Comparison 61
• 4.2.3 Capacitively Driven Simultaneous Bidirectional Signaling 63
• 4.3 CD-SBD Transceiver Implementation 67
• 4.3.1 System Overview 67
• 4.4 PVT/Mismatch tracking 70
• 4.5 Quadrature generator with QEC/DCC 73
• 4.6 Calibration 77
• 4.6.1 Offset calibration 77
• 4.6.2 Initial WDC and WXT C calibration 77
• 4.6.3 SER/DES latency calibration 78
• 4.7 Measurement 79
• 4.7.1 Test Channel Implementation 79
• 4.7.2 Performance of CD-SBD and PVT/Mismatch Tracking 80
• 5 Conclusion 85
• Abstract (In Korean) 96