게이트 저항을 이용한 상승 및 하강 시간 제어에 따른 스위칭 노이즈 고조파 저감 기반 EMI 개선의 이론적 분석

다국어 초록 (Multilingual Abstract)

M.S. Thesis

Theoretical Analysis of EMI Improvement Based on Switching Noise Harmonic Reduction Through Rising and Falling Time Control Using Gate Resistance

JEONGHYEON CHEON
Department of Automotive Engineering
Graduate School
Yeungnam University
Supervised by Professor Dongwook Kim
ABSTRACT
Electromagnetic interference (EMI) has become a significant issue as electronic devices become more integrated and achieve high performance. In order to operate at high performance in an integrated system, a high-frequency clock signal is essential to enhance processing speed. However, the harmonic component of the clock signal or gate signal is one of the major EMI sources that can cause peripheral devices to malfunction and affect their stability and reliability. In this paper, harmonic component analysis of the MOSFET gate signal which depends on gate resistance is conducted. Based on theoretical analysis using Fourier series expansion, gate resistance contributes to harmonic components that are determined by the rising and falling times of a gate signal. Simulation and measurement are conducted using a buck converter as a practical application. The theoretical analysis is validated by simulation and experimental results demonstrate that the magnitude of the harmonics is reduced because increasing the gate resistance extends the rising and falling times.

목차 (Table of Contents)

• 제1장 서론 1
• 1.1 연구 배경 1
• 1.2 기존 연구 사례 2
• 1.3 연구 목표 4
• 제2장 MOSFET 소자 기반 이론적 모델링 5
• 2.1 이론적 모델링을 위한 MOSFET 등가 회로 5
• 2.2 게이트-소스 전압의 과도 응답 10
• 2.3 푸리에 계수를 통해 계산된 주파수 성분 18
• 제3장 시뮬레이션을 통한 검증 24
• 3.1 Low-side buck converter로 구성된 시뮬레이션 셋업 24
• 3.2 Low-side buck converter 시뮬레이션 결과 26
• 제4장 실험을 통한 검증 28
• 4.1 제작된 low-side buck converter와 측정 셋업 28
• 4.2 실험 결과 31
• 제5장 고찰 37
• 제6장 결론 38
• 참고문헌 39
• Abstract 49