A Study on the Hafnia-Based Ferroelectric Device and Oxide-Semiconductor Channel Transistor for 3D Memory Applications = 3D 메모리 응용을 위한 산화물 채널/high-k 유전체 구조 트랜지스터 연구

다국어 초록 (Multilingual Abstract)

The rapid advancement of artificial intelligence and data-centric applications has intensified the need for memory technologies with higher performance, lower power consumption, and scalable integration. Conventional dynamic random-access memory (DRAM) scaling is increasingly constrained by power, noise, and lithographic complexity, whereas three-dimensional (3D) integration offers a promising path to expand capacity and bandwidth without enlarging the footprint. However, the stringent thermal budget (<400 °C) in stacked device fabrication limits the use of conventional crystalline silicon channels, motivating exploration of ferroelectric HfO₂ and amorphous oxide semiconductors as low-temperature-processable alternatives. This dissertation begins with ferroelectric capacitors (FeCAPs) to systematically investigate the influence of Al₂O₃ atomic layer deposition (ALD) sub-cycles on the ferroelectric switching behavior of a 10-nm-thick HfO₂ matrix. Spontaneous remnant polarization (2Pr) was achieved when three to four Al₂O₃ cycles were incorporated and annealed after W top electrode (TE) deposition, whereas excessive doping induced leakage, open hysteresis loops, and limited endurance of ~10⁵ cycles. Notably, concentrating the Al₂O₃ layers near the lower region of HfO₂ yielded an enhanced 2Pr of ~9 μC/cm², achieving up to a threefold improvement compared to uniform doping. These results highlight that the mechanical stress induced by the W TE in the upper region and the dopant-induced stress concentrated near the bottom collectively generated a uniform stress distribution across the HfO₂ film. This cooperative stress promoted an even ferroelectric orthorhombic (o)-phase transformation throughout the layer, enabling a larger fraction of dipoles to participate in polarization switching. Building on these insights from two-terminal capacitor structures, the research was extended to three-terminal ferroelectric field-effect transistors (FeFETs), which share the same principle of utilizing ferroelectric polarization for memory operation. To overcome the limited memory window (MW) of oxide-channel FeFETs, interfacial channel engineering was introduced by selectively doping p-type Si (p-Si) at the InZnO (IZO) interface. Analysis across FeCAPs and TFTs revealed that p-Si not only modulates HZO polarization but also tunes IZO channel conduction. This approach effectively suppressed electron accumulation near the ferroelectric/channel boundary without inducing bulk charge trapping, thereby enlarging the MW to 2.3 V—more than double that of undoped devices—while maintaining stable program/erase operation. Following the FeFET studies, the role of p-Si channel doping was further examined in ultrathin indium–zinc–oxide (IZO) thin-film transistors (TFTs) to decouple and verify its direct impact on channel properties. The undoped IZO TFT exhibited a threshold voltage (VT) of –3.5 V and a subthreshold swing (SS) of 199 mV/dec, indicating excessive free carrier density and interface traps. In contrast, incorporation of p-Si into the IZO channel (3 W p-Si:IZO) with 3 W sputtering power, suppressed excess electron carriers and improved device performance, increasing VT to –2.3 V and reducing SS to 122 mV/dec. X-ray photoelectron spectroscopy confirmed an enhanced O–H bond signal in the doped channel, suggesting that hydrogen-related traps originating from the HfO₂ dielectric were effectively passivated. Consistently, the trap density extracted from SS was reduced to 6.4×10¹³ eV⁻¹·cm⁻². As a result, the optimized p-Si:IZO TFT exhibited robust reliability, with VT shifts of only 0.3 V and 0.4 V under positive bias stress (PBS) and positive bias temperature stress (PBTS, 85 °C), respectively. Furthermore, stable operation was demonstrated at cryogenic temperatures down to –170 °C, with VT improved to –1.1 V and SS steepened to 105 mV/dec, confirming the suitability of oxide semiconductors for low-temperature integration. Finally, a comparative study of FeFETs and TFTs unveiled the critical role of channel properties in determining the MW of ferroelectric devices. Reference TFTs with an HfO₂ dielectric layer exhibited a VT of –3 V and an SS of 265 mV/dec with hysteresis- free behavior. In contrast, ferroelectric dipole switching in FeFETs shifted VT between – 1 V and –3 V, yielding an MW of ~2 V with a steepened SS of 250 mV/dec. These results indicate that while ferroelectric polarization drives threshold modulation, the actual extent of the MW is strongly coupled to the intrinsic electronic response of the oxide channel, highlighting the necessity of deliberate channel engineering for reliable memory operation.

목차 (Table of Contents)

• I. Introduction 1
• 1.1 3D integration memory 1
• 1.2 Hafnia-based ferroelectric devices for memory applications 2
• 1.3 Oxide-semiconductor channels for 3D applications 3
• 1.4 Thesis outline 4
• 1.5 References 5
• II. Al doped HfO2 ferroelectric capacitor 8
• 2.1 Ferroelectricity as function of Al dopant distribution within the HfO2 layer 8
• 2.1.1 Research background 7
• 2.1.2 Results and discussion 9
• 2.1.3 Conclusion 17
• 2.1.4 References 18
• III. Oxide channel ferroelectric field-effect transistor (FeFET) 28
• 3.1 Enhancing IZO FeFET memory window via p-Si interface doping 28
• 3.1.1 Research background 28
• 3.1.2 Results and discussion 29
• 3.1.3 Conclusion 36
• 3.1.4 References 37
• IV. Oxide channel thin-film transistor (TFT) 45
• 4.1 Reliability enhancement of ultrathin IZO TFTs by p-Si doping 45
• 4.1.1 Research background 45
• 4.1.2 Results and discussion 47
• 4.1.3 Conclusion 55
• 4.1.4 References 56
• Ⅴ. Relationship between FeFET and TFT 65
• 5.1 Unveiling channel effects in HfZrO₂ FeFETs with p-Si:IZO channel 65
• 5.1.1 Research background 65
• 5.1.2 Results and discussion 67
• 5.1.3 Conclusion 74
• 5.1.4 References 75
• Ⅵ. Conclusion 83
• Abstract in Korean 86