A Study on Synaptic Device Design Using Resistive Switching Memory for Next-Generation Computing Platforms = 차세대 컴퓨팅 플랫폼을 위한 저항성 스위칭 메모리를 활용한 시냅스 소자 설계 연구

다국어 초록 (Multilingual Abstract)

The explosive growth of data-centric applications in artificial intelligence, edge computing, and the Internet of Things has exposed the memory–processor bottleneck of von Neumann architectures. Neuromorphic computing, which emulates the parallel and event-driven information processing of the brain, offers a path toward energy-efficient systems; however, its success hinges on analog synaptic devices that deliver linear, symmetric, and reliable weight updates. Among emerging memories, resistive random- access memory (RRAM) is attractive for its CMOS compatibility, speed, and multilevel capability, yet filamentary switching often yields non-ideal updates, variability, sneak- path currents in cross-point arrays, and degraded behavior at cryogenic temperatures. This dissertation develops RRAM synapses addressing those hurdles across three device directions. First, a selector-less Al2O3/HfO2 RRAM is introduced, where an ultrathin Al2O3 layer serves as a built-in exponential resistor to impart strong I–V nonlinearity that suppresses sneak currents while enabling gradual two-step set switching validated by real-time transient analysis. The device achieves linear and symmetric weight updates under identical pulses, preventing half-select disturbances and delivering high handwritten-digit recognition accuracy in IBM AIHWKIT-based simulations. Second, a fully sputtered HfOy/HfOx bilayer RRAM is developed to engineer oxygen- vacancy distributions for reliable, fast analog operation. The sub-stoichiometric HfOx switching layer and oxygen-rich HfOy interface layer jointly provide uniform D2D/C2C behavior, stable multilevel retention, and linear updates with 100-ns pulse widths, with transient measurements indicating ~8-ns switching delay and pJ-level energy per update; system simulations confirm high classification accuracy with efficient training. Third, a cryogenic RRAM analog synapse (CRAS) based on the sputtered HfOy/HfOx stack is demonstrated at 90 K. By reset engineering to form partially connected filaments, the device maintains linear potentiation under identical 50-ns pulses and robust multilevel retention, addressing the tendency toward abrupt, field-driven switching in low- temperature operation. Taken together, these selector-less design principles, sputtered-stack vacancy engineering, and cryogenic operation strategies establish practical guidelines for scalable, low-power RRAM synapses suited to next-generation neuromorphic accelerators and quantum-compatible cryo-computing platforms.

목차 (Table of Contents)

• I. Introduction 1
• 1.1 Bottleneck of von Neumann and alternative computing paradigms 1
• 1.1.1 Neuromorphic computing system 2
• 1.1.2 Requirement of cryo-computing platforms 3
• 1.2 Resistive random-access memory (RRAM) 4
• 1.2.1 Fundamentals of RRAM 4
• 1.2.2 Challenges in RRAM-based synaptic devices 5
• 1.3 Thesis outline 6
• 1.4 References 7
• II. Selector-Less RRAM 13
• 2.1 Improved synaptic behavior in selector-less RRAM with Al2O3 built-in resistor 13
• 2.1.1 Research background 13
• 2.1.2 Experiments 15
• 2.1.3 Results and discussion 16
• 2.1.4 Conclusion 25
• 2.1.5 References 25
• III. Sputtered HfOx-based RRAM 42
• 3.1 Robust and reliable synaptic operation in HfOy/HfOx bilayer RRAM 42
• 3.1.1 Research background 42
• 3.1.2 Experiments 44
• 3.1.3 Results and discussion 46
• 3.1.4 Conclusion 54
• 3.1.5 References 55
• IV. Cryogenic RRAM Analog Synapse (CRAS) 75
• 4.1 Reset-Controlled Linear Potentiation in Cryogenic RRAM 75
• 4.1.1 Research background 75
• 4.1.2 Experiments 77
• 4.1.3 Results and discussion 77
• 4.1.4 Conclusion 82
• 4.1.5 References 82
• V. Conclusion 92
• Abstract in Korean 94