Device-Independent Synthesis of Ternary Logic Circuits:An RTL-Based Approach = 디바이스 독립적인 삼진논리회로를 위한 RTL 기반 삼진 논리 합성 방법론

다국어 초록 (Multilingual Abstract)

Ternary logic circuits are gaining significant attention as a potent alternative that can extend the technological advancements of binary logic circuits. Currently, research on ternary logic is primarily focused on two aspects: 1) the design of specific ternary circuits such as adders, multipliers, and CPU, and 2) the proposal of design methodologies that enable circuit implementation using specific ternary devices. However, to implement large-scale ternary logic circuits, there is a critical need for a synthesis methodology applicable to various ternary devices and Hardware Description Languages (HDLs).

Accordingly, this study proposes: 1) a synthesis methodology from ternary RTL to a gate-level netlist, 2) a ternary logic syntax based on Verilog HDL, and 3) the first GT-LOGIC (Generic Ternary Logic) library and mapping strategy for logic synthesis. The proposed RTL-level synthesis method achieves a synthesis result with an average 63.39% reduction in cell count compared to conventional MUX-based synthesis. Furthermore, we demonstrate that this methodology can successfully synthesize ternary logic across various ternary devices, including CNTFET, T-CMOS, and DEPFETs.

목차 (Table of Contents)

• I. Introduction 1
• II. Motivation 3
• 2.1 Necessity of Device-independent Synthesis 3
• 2.2 Necessity of Logic Gate-based Synthesis 4
• 2.3 Necessity of Designer-free Synthesis 5
• 2.4 Necessity of RTL-based Synthesis 6
• III. Background 7
• 3.1 The 'Half-logic' and Its Implication 7
• 3.2 1-input Ternary Logic Gates 8
• 3.3 2-input Ternary Logic Gates 9
• 3.4 The Core Logic Library in Logic Synthesis 10
• IV. Ternary Logic Synthesis (1) - The GT-LOGIC 12
• 4.1 1-input logic gates for GT-LOGIC 13
• 4.2 2-input logic gates for GT-LOGIC: (1) trivial ternary logic functions 15
• 4.2.1 2-input logic gates for GT-LOGIC: (2) The Inductive Divergence Algorithm 17
• 4.3 Logic gates with More than two Inputs for GT-LOGIC 19
• 4.4 Current Status of GT-LOGIC 20
• V. Ternary Logic Synthesis (2) - The RTL 23
• 5.1 Gate/Transistor-level RTL 23
• 5.2 Data Flow-level RTL 25
• 5.3 Behavioral-level RTL 27
• 5.3.1 Case construct 28
• 5.3.2 If-else/If-else-if construct 29
• 5.3.3 Always @ construct 30
• VI. Experimental Results 32
• 6.1 Ternary Benchmark 32
• 6.2 Flow of the Synthesis Process 33
• 6.3 Validating ternary RTL and the Synthesized Netlist 34
• 6.4 Experimental Results and Discussions 35
• 6.5 Future Work 37
• VII. Conclusion 41
• References 42