Study on the effects of interface traps on electrical transport in WSe₂ field-effect transistors

다국어 초록 (Multilingual Abstract)

Two-dimensional (2D) semiconductors have attracted significant attention as promising channel materials for next-generation electronics, owing to their atomically thin bodies, excellent electrostatic gate control, and the ability to form high-quality van der Waals (vdW) interfaces. However, the absence of dangling bonds and the extremely large surface-to-volume ratio also render 2D devices highly vulnerable to interface traps, defects, and contact-related limitations. These issues negatively affect threshold swing, carrier mobility, hysteresis, and overall device reliability, posing a major obstacle to scaling 2D field-effect transistors (FETs). This dissertation investigates the electrical properties of WSe2-based 2D FETs with a strong emphasis on understanding and engineering interface traps. First, a systematic analysis of interface trap density (Dit) is performed using capacitance–voltage (C–V), conductance–voltage (G–V), and subthreshold swing (SS) techniques across various WSe2 thicknesses. The study reveals that trap states are strongly dependent on both channel thickness and carrier polarity, and that Dit values near mid-gap dominate electrical behavior. Thinner WSe2 channels show larger frequency dispersion and stronger trap activity, highlighting the critical role of dielectric/2D interfaces in determining device performance. These insights establish a quantitative understanding of trap distributions and their impact on WSe2 FET characteristics.
In the second part, the dissertation focuses on the development of defect-engineered vertical field-effect transistors (VFETs), which offer a scalable path toward ultra-short channel lengths and 3D integration. Despite their architectural advantages, VFETs commonly suffer from metal diffusion, Fermi-level pinning, and uncontrolled off-state tunneling currents at metal/2D interfaces. To address these challenges, this work introduces a selective plasma oxidation technique that converts the top WSe2 layer into a WOx tunneling barrier. Combined with a vdW bottom-contact architecture using graphene and high work function NbSe2 as contact electrodes, the resultant VFET exhibits defect-free interfaces, suppressed direct tunneling, and significantly improved hole injection. As a result, the fabricated p-type VFETs achieve high on/off current ratios of 102 ~ 105 for channel thicknesses of 1-5 layers representing one of the highest values reported for p-type vertical TMDC FETs.
Overall, this dissertation provides a comprehensive understanding of interface trap mechanisms in 2D materials and introduces a practical contact-engineering strategy using plasma-treated WOx for high-performance vertical devices. The findings offer valuable guidelines for optimizing interface quality, minimizing trap-induced degradation, and enabling highly scalable 2D semiconductor devices for future beyond-CMOS applications.

목차 (Table of Contents)

• Chapter 1. Introduction 1
• 1.1. Two-dimensional (2D) materials 1
• 1.2. 2D materials for Beyond-CMOS scaling 3
• 1.3. Interface traps and defects in 2D materials 5
• 1.4. Electrical characterization techniques for 2D FETs 8
• 1.5. Methods to determine the interface trap density 10
• 1.5.1. Capacitance-Voltage method 10
• 1.5.2. Conductance-Voltage method 11
• 1.5.3. Subthreshold swing equation method 12
• 1.6. Scope and objective of a dissertation 14
• Chapter 2. Analysis of Interface Trap states in WSe2 FET 15
• 2.1. Defects and Interface traps in WSe2 devices 15
• 2.2. Device fabrication and characterization 17
• 2.3. Capacitance-Voltage measurement 20
• 2.3.1. Extraction of traps density by C-V measurements 22
• 2.3.2. Thickness dependent C-V measurements 23
• 2.3.3. Frequency dispersion in hBN/WSe2 based capacitors 27
• 2.4. Conductance-Voltage measurement 29
• 2.4.1. Thickness dependent G-V measurements 30
• 2.5. Interface trap density 32
• 2.5.1. Energy spectrum of Dit for p-type, ambipolar and n-type WSe2 34
• 2.6. Subthreshold swing equation 36
• 2.6.2. Electrical characterization of monolayer vdW contacted WSe2 FET 38
• 2.6.3. Electrical characterization of different thickness vdW contacted WSe2 FET 40
• 2.6.4. Electrical Hysteresis of vdW contacted WSe2 FET 42
• 2.6.5. Temperature-dependent electrical characteristics of WSe2 FET 43
• 2.6.6. Temperature-dependent output curve of monolayer device 45
• 2.6.7. Temperature-dependent electrical properties 46
• 2.6.8. Electrical stability test over time 51
• 2.6.9. Leakage current 53
• Chapter 3. Defect-Engineered Vertical WSe2 FETs with High On/Off Ratio via Plasma Oxidation 55
• 3.1. Transition to Vertical FETs in the Post-Moore Era: Scaling Limits 55
• 3.2. Fundamentals and Challenges of Vertical FET 58
• 3.2.1. Comparison between Planar and Vertical FET Architectures 60
• 3.2.2. Interface Defects and Performance Limitations in VFETs 61
• 3.2.3. Metal Diffusion and Its Impact on Vertical Devices 63
• 3.2.4. Fermi-Level Pinning Effects in 2D Vertical Contacts 64
• 3.3. Device fabrication and characterization 66
• 3.3.1. Transmission electron microscopy 68
• 3.3.2. Energy-dispersive X-ray spectroscopy 70
• 3.3.3. Raman spectroscopy 71
• 3.3.4. X-ray photoelectron spectroscopy 72
• 3.3.5. Atomic force microscopy 75
• 3.4. Effect of Plasma treatment on 2D materials 76
• 3.5. Effects of WOx on 2D Vertical FET performance 80
• 3.5.1. Graphene/WSe2/NbSe2 VFETs and its transfer characteristics 80
• 3.5.2. Transfer characteristics of the devices with graphene/WSe2/WOx/Pt contacts 81
• 3.5.3. Transfer characteristics of the devices with graphene/WSe2/WOx/NbSe2 contacts 83
• 3.5.4. Band diagram 85
• 3.5.5. Output characteristics of the vertical FET 88
• 3.5.6. Off-state current comparison for vertical FET 89
• 3.5.7. Gate leakage (SiO2) current of 1L WSe2 channel device. 90
• 3.6. Comparative analysis of the on/off current ratio 91
• 3.7. Conclusion 92
• Chapter 4. Conclusion 93
• 4.1. Summary 93
• 4.2. Future perspectives 95