Low-power program and erase optimization in 3D NAND flash with enhanced GIDL erase and hot-carrier injection program

다국어 초록 (Multilingual Abstract)

This study investigates the structural and electrical characteristics of vertical NAND (V-NAND) flash memory to improve the performance and reliability of next-generation nonvolatile memory devices. The research focuses on two key operation mechanisms: Gate-Induced Drain Leakage (GIDL)-assisted erase and Hot-Carrier Injection (HCI)-based program. Both mechanisms were analyzed using calibrated Technology Computer-Aided Design (TCAD) simulations to clarify the relationship between device geometry, electric field distribution, and charge transport behavior.
In the erase operation, a Surrounded Bit-Line (BL) pad structure was examined to enhance hole generation efficiency through the GIDL mechanism. Although this structure increases the band-to-band tunneling (BTBT) rate and accelerates erase speed, a saturation phenomenon occurs when the number of GIDL transistors becomes excessive due to mutual interference of generated holes. To overcome this limitation, convex and concave wordline geometries were introduced and systematically compared. The convex profile concentrated the local electric field and improved erase efficiency, whereas the concave profile dispersed the field and suppressed lateral charge migration, leading to enhanced data retention. The optimal convex depth of approximately one nanometer was identified as the condition that provides a balanced trade-off between erase speed and retention characteristics.
In the program operation, the conventional Fowler–Nordheim (FN) tunneling method was replaced by a bi-lateral Hot-Carrier Injection (HCI-BiPGM) scheme employing symmetrically arranged switch wordlines on both sides of the program wordline. This configuration formed a balanced lateral electric field and a uniform floating-channel potential, resulting in even charge injection and reduced program disturbance near the drain-select line. Simulation results confirmed that the HCI-BiPGM method achieved approximately sixty percent higher programming efficiency than the FN tunneling scheme while maintaining improved uniformity and device reliability.
Through the combined optimization of the GIDL-based erase structure and the HCI-based program scheme, this work establishes an integrated design approach for high-density and high-reliability V-NAND flash memory. The findings provide valuable insight into structural and electrical design strategies that can guide the development of future nonvolatile memory technologies.

국문 초록 (Abstract)

본 연구는 차세대 비휘발성 메모리의 성능과 신뢰성 향상을 위해 V-NAND 플래시 메모리의 구조적·전기적 특성을 체계적으로 분석하였다. Erase 동작에서는 GIDL 메커니즘 기반의 Surrounded BL PAD 구조를 활용해 밴드 간 터널링을 촉진하고 소거 속도를 향상시켰다. 다만 GIDL 트랜지스터 수 증가에 따른 정공 간섭 문제를 해결하기 위해 볼록(convex)·오목(concave) 워드라인 구조를 비교한 결과, 약 1 nm 깊이의 볼록 구조가 소거 속도와 데이터 유지 특성의 최적 균형을 달성함을 확인하였다. program 동작에서는 기존 FN-tunneling 대신 양방향 핫 캐리어 주입(HCI-BiPGM) 방식을 제안하였다. 이 방식은 대칭 전계 형성으로 균일한 전하 주입과 Program disturb 억제를 실현하여, FN-tunneling 대비 약 60 % 높은 프로그램 효율과 향상된 신뢰성을 보였다.
따라서 본 연구는 GIDL 기반 소거 구조와 HCI 기반 프로그램 방식을 각각 최적화함으로써, 고집적·고신뢰성 V-NAND 플래시 메모리 설계를 위한 통합적 설계 방향을 제시하였다.

목차 (Table of Contents)

• Chapter 1. Introduction 1
• 1.1. Research Background and Motivation 1
• 1.2. GIDL-assisted Erase by using Surrounded BL PAD Structure and Hot Carrier Injection Programming Method 3
• Chapter 2. Analysis of GIDL-assisted Erase in Surrounded BL PAD Structure 6
• 2.1. Device Structure and Calibration method 6
• 2.2. Limiations of Surrounded BL pad Structure 10
• 2.3. Impact of Structural Geometry on Erase and Retention Characteristics 12
• Chapter 3. Self-Boosting Hot Carrier injection programming Method 25
• 3.1. Device Structure and Calibration method 25
• 3.2. Uni-lateral HCI programming method 29
• 3.3. Bi-lateral HCI programming and Inhibit method 35
• Chapter 4. Conclusion 44
• References 45
• Korean Abstract 50