CORD : in-storage compression for enhancing read performance and lifetime of NAND flash-based SSDs

다국어 초록 (Multilingual Abstract)

The rapid growth of data-intensive workloads, such as deep learning and big-data analytics, demands NAND Flash-based SSDs (Solid-State Drives) to simultaneously achieve unprecedented levels of high capacity, low latency, and improved reliability. However, modern SSDs struggle with read disturbance, a phenomenon that causes interference in NAND Flash cells and leads to subsequent read errors. To address these errors, conventional SSD controllers rely heavily on repeated read-retry operations, which significantly increase read latency and accelerate device wear-out.

In this paper, we introduce CORD (COmpression-assisted Read Disturbance mitigation), a novel framework that mitigates the read disturbance by strategically leveraging data compression. CORD consists of two core techniques: SBA (Selective Bitline Activation) and SCPP (Shifted Cyclic Placement Policy). SBA stores compressed data in a reduced portion of NAND Flash page, allowing the SSD controller to deactivate unused cells during read operations. This selective bitline activation limits the number of Flash cells exposed to read related voltages such as VPASS, thereby reducing the number of cells affected by read disturbance. As a result, SBA lowers the likelihood of bit errors and significantly reduces the frequency of read-retry events. To further alleviate read disturbance and prevent localized stress accumulation, SCPP cyclically shifts compressed data across wordlines to evenly distribute bitline activity.

Our experimental results demonstrate that CORD reduces the number of read-retry operations by up to 99.6% and improves read performance by up to 57.2%. Under intensive read workloads, CORD remarkably extends SSD lifetime from 427 days to 2012 days. The hardware implementation of CORD introduces only 0.13% additional area and 0.98% extra power consumption in the SSD controller.

국문 초록 (Abstract)

최근 딥러닝 및 빅데이터 분석과 같은 데이터 집약적인 워크로드가 급증함에 따라, NAND flash 기반 SSD는 고용량, 저지연, 그리고 높은 신뢰성을 동시에 달성해야 하는 과제를 안고 있다. 그러나 현대의 SSD는 read disturbance라는 문제에 직면하고 있으며, 이는 NAND Flash 셀 간 간섭으로 인해 읽기 오류를 유발한다. 이러한 오류를 해결하기 위해 기존 SSD 컨트롤러는 반복적인 read-retry 동작에 의존하고 있으나, 이는 읽기 지연을 크게 증가시키고 디바이스의 마모를 가속화시킨다.

본 논문에서는 데이터 압축을 전략적으로 활용하여 read disturbance를 완화하는 새로운 프레임워크인 CORD (COmpression-assisted Read Disturbance mitigation)를 제안한다. CORD는 두 가지 핵심 기술로 구성된다: SBA (Selective Bitline Activation)와 SCPP (Shifted Cyclic Placement Policy)이다. SBA는 압축된 데이터를 NAND flash 페이지의 축소된 영역에 저장함으로써, SSD 컨트롤러가 읽기 시 사용되지 않는 셀들을 비활성화할 수 있도록 한다. 이러한 선택적 비트라인 활성화는 VPASS 와 같은 읽기 관련 전압에 노출되는 셀의 수를 제한하여 read disturbance의 영향을 받는 셀 수를 줄인다. 그 결과 SBA는 비트 오류 가능성을 낮추고 read-retry 발생 빈도를 현저히 감소시킨다. 또한, SCPP는 압축 데이터를 워드라인 간에 순환 배치하여 비트라인 활성화를 고르게 분산시킴으로써 국소적인 스트레스 누적을 방지하고 read disturbance를 더욱 완화한다.

실험 결과, CORD는 read-retry 동작 횟수를 최대 99.6%까지 줄이고, 읽기 성능을 최대 57.2%까지 향상시킨다. 고강도 읽기 워크로드 환경에서는 SSD 수명을 427일에서 2012일까지 대폭 연장시킨다. 또한, CORD의 하드웨어 구현은 SSD 컨트롤러 면적의 0.13%, 전력 소모의 0.98%만을 추가로 요구하여, 매우 효율적인 설계임을 입증한다.

목차 (Table of Contents)

• 1. Introduction 1
• 2. Background 6
• 2.1. Overview of NAND Flash-based SSDs 6
• 2.2. Error Vulnerability of NAND Flash 8
• 2.3. Read Disturbance 10
• 2.4. Read Retry 11
• 3. Motivation 12
• 3.1. Impact of Read Retry on SSD Lifetime 12
• 3.2. Impact of Read Retry on Read Performance 14
• 3.3. Data Compression: An Enabler for SSD Enhancements 15
• 4. CORD: Compression-Assisted Read Disturbance Mitigation 18
• 4.1. Selective Bitline Activation 19
• 4.2. SSD Architecture with Compression Support 21
• 4.3. Metadata Management 22
• 4.4. Compression and Decompression Workflow Details 24
• 4.5. Read Operation with Selective Bitline Activation 25
• 4.6. Protocol Support for Selective Bitline Activation 26
• 4.7. Field-Based Data Allocation for ECC Compatibility 27
• 4.8. Shifted Cyclic Placement Policy 29
• 4.9. SCPP with 4 KB L2P Mapping 31
• 5. Design Considerations for CORD SSDs 32
• 5.1. Host vs. SSD Compression 32
• 5.2. Selection of Compression Algorithm 32
• 5.3. Trade-off Between Capacity Optimization and Design Complexity 33
• 5.4. Handling Incompressible Data (Fallback Behavior) 34
• 5.5. Applicability to High-Density NAND Flash 35
• 6. Evaluation 36
• 6.1. Simulation Setup 36
• 6.2. Read Retry Count 37
• 6.3. Performance Improvement 40
• 6.4. Lifetime Improvement 41
• 6.5. A quantitative analysis of the effects of SBA and SCPP 43
• 6.6. Hardware Overheads 45
• 7. Related Work 47
• 8. Conclusion 49