Advanced CFET SRAM architecture : performance and stability analysis

국문 초록 (Abstract)

본 연구에서는 CFET(Complementary FET) 기반 SRAM의 고집적화 및 제조 신뢰성 확보를 위해 두 가지 핵심 구조를 제안하고 성능을 분석하였다. 첫째, Front-Side Vss와 Back-Side Bitline(FS_Vss & BS_BL) 배선 구조와 PR-GATE(partially recessed gate) 기법을 도입하여 Tall Via를 제거한 CFET 6T SRAM 구조를 제시한다. 해당 구조는 BL 및 Vss 경로에서 Tall Via로 인한 저항 및 기생 커패시턴스를 효과적으로 제거하여 읽기/쓰기 지연 및 동작 에너지 특성을 개선하며, 기존 CFET 셀과 동일한 안정성을 확보하였다.
둘째, 셀 면적 스케일링을 극대화하기 위해 기존 2-Stack CFET 대비 면적을 27% 감소시키는 3-Stack CFET SRAM 구조를 제안하였다. 3D TCAD 및 BSIM-CMG 기반 압축 모델을 활용하여 소자-회로 연동 평가를 수행한 결과, Metal Pitch 감소에 따른 BL 기생 커패시턴스 증가로 일부 AC 지연 증가가 나타났으나, SNM 및 WRM 안정성은 기존 구조와 유사하게 유지되었다. 또한, 저저항 금속 도입 및 배선 재구성하여 RC overhead를 보완하면 향후 셀 스케일링 이점을 지속적으로 확보할 수 있는 구조를 제시하였다.
종합적으로, 본 연구에서 제시한 Tall Via 제거 및 3-Stack 적층 구조는 CFET 기반 SRAM의 성능, 제조성 및 스케일링 잠재력을 동시에 확보할 수 있는 설계 방향임을 입증하였으며, 차세대 sub-2 nm 로직 공정 환경에서 유력한 SRAM 구현 전략을 제시한다.

다국어 초록 (Multilingual Abstract)

As CMOS scaling approaches fundamental physical and design limitations at sub-2-nm technology nodes, complementary field-effect transistor (CFET) architectures have emerged as a promising device platform for extending Moore’s law in future high-density and low-power memory systems. In this work, we present a comprehensive investigation of CFET-based 6T SRAM scaling through two synergistic innovations: (i) a tall-via-less CFET SRAM cell architecture enabled by asymmetric front-side/back-side power and signal routing, and (ii) a vertically integrated three-stack CFET SRAM topology for extreme area reduction.
First, we propose a tall-via-less CFET 6T SRAM utilizing a Front-Side Vss and Back-Side Bitline (FS_Vss & BS_BL) routing strategy together with a partially recessed gate structure, completely eliminating conventional tall-via (TV) connections. This design addresses critical challenges associated with tall-via processing—including high via resistance, parasitic capacitance, and manufacturability obstacles—by spatially separating power delivery and read/write data paths. Comprehensive SPICE-level circuit simulations calibrated with experimentally validated TCAD and BSIM-CMG compact models demonstrate that the proposed architecture significantly reduces bitline and ground-rail parasitics, achieving improvements of up to 4.6% in read delay, 3.4% in write delay, and 13.7%/6.5% reductions in read/write energy consumption, respectively, while preserving RSNM and BWTV stability margins relative to a conventional CFET baseline.
In parallel, we explore an advanced three-stack CFET SRAM architecture to further push cell density. The proposed multi-stack topology achieves a 27% reduction in cell footprint compared to conventional two-stack CFET SRAM due to reduced metal pitch and optimized vertical integration. Detailed 3D TCAD evaluation and compact-model-driven circuit analysis reveal that aggressive pitch scaling leads to a ~1.6× increase in bitline capacitance and moderate degradation in AC performance; however, other key metrics, including RSNM and BWTV, remain comparable owing to minimal change in bitline resistance. Design trade-offs further indicate that the use of emerging low-resistivity metals (e.g., Ru) and alternate metal routing strategies can suppress RC penalties while preserving the full scaling benefit.
Taken together, the two CFET-SRAM innovations presented here offer a cohesive pathway toward high-performance and manufacturable memory solutions at deeply scaled technology nodes. The results confirm that eliminating tall vias and leveraging multi-stack vertical integration can jointly enable significant performance gains, energy efficiency, and density improvement, positioning CFET-based SRAM as a key enabler for future logic-memory co-integration in beyond-CMOS computing systems.

목차 (Table of Contents)

• Abstract
• Chapter 1. INTRODUCTION
• Chapter 2. Simulation Method
• 1. Simulation Environment : Tall Via(TV)-Less CFET SRAM
• 2. Simulation Environment : Three-stacked CFET SRAM
• Chapter 3. Simulation Results
• 1. Results and Discussion : Tall Via(TV)-Less CFET SRAM
• 2. Results and Discussion : Three-stacked CFET SRAM
• Chapter 4. Conclusion
• References
• 논문요약