디지털 주파수 고정 루프를 가지는 1 〜 3.2 GHz 서브 샘플링 위상 고정 루프 = 1 〜 3.2 GHz Sub-sampling Phase-locked Loop with Digital Frequency-locked Loop

다국어 초록 (Multilingual Abstract)

This thesis presents the design of a sub-sampling phase-locked loop (SSPLL) that supports a wide output frequency range from 1 to 3.2 GHz. The proposed SSPLL consists of a sub-sampling phase detector (SSPD), a charge pump, a loop filter, a voltage-controlled oscillator (VCO), a pulse generator, and a digital frequency-locked loop (FLL). The digital FLL is additionally integrated to ensure stable frequency acquisition over the wide operating frequency range. The SSPD, which fundamentally receives RF signals as input signals, uses a CML buffer as its input stage to maintain low phase detection gain even for square wave input signals. Additionally, the pulse generator supports robust operation of the SSPLL by varying the pulse width to compensate for KVCO drift caused by changes in the output frequency. The VCO adopts a ring oscillator structure to cover the entire target frequency range from 1 to 3.2 GHz. It is primarily controlled by a 9-bit digital code generated by the operation of a digital FLL to perform coarse locking to the frequency. Subsequently, it is controlled by an analog control voltage determined based on the output of the SSPD for fine phase locking.
The proposed SSPLL is implemented by using a 65-nm CMOS process with a supply voltage of 1.2 V. The designed SSPLL has an area of 276.39 μm × 294.56 μm, of which the logic added for the digital FLL occupies an area of 42.98 μm × 64.33 μm. It generates clocks from 1 to 3.2 GHz using a 20 MHz reference clock. The designed SSPLL consumes 5.79 mW of power when generating a 1.8 GHz output, with peak-to-peak and rms time jitter of 7.23 ps and 1.39 ps, respectively. The proposed SSPLL simultaneously achieves a wide locking range using the digital FLL and low in-band phase noise using the SSPD architecture, making it suitable for high-speed and wide-frequency-range applications.

목차 (Table of Contents)

• 제 1 장 서 론
• 1.1 연구 배경
• 1.2 고속 인터페이스용 PLL의 역할 및 기존 CPPLL 한계
• 1.3 SSPLL의 장점 및 한계
• 제 2 장 CPPLL과 SSPLL
• 2.1 전하 펌프 위상 고정 루프(Charge pump phase-locked loop)
• 2.1.1 전하 펌프 위상 고정 루프
• 2.1.2 전하 펌프 위상 고정 루프 잡음
• 2.2 서브 샘플링 위상 고정 루프(Sub-sampling phase-locked loop)
• 2.2.1 서브 샘플링 위상 고정 루프
• 2.2.2 서브 샘플링 위상 고정 루프 문제점
• 제 3 장 디지털 FLL을 포함한 SSPLL 설계
• 3.1 설계 사양
• 3.2 전체 구조
• 3.3 상세 설계
• 3.3.1 디지털 주파수 고정 루프(Frequency-locked loop)
• 3.3.2 위상 검출기(Sub-sampling phase detector)
• 3.3.3 펄스 발생기(Pulser)
• 3.3.4 전하 펌프(Charge pump)
• 3.3.5 루프 필터(Loop filter)
• 3.3.6 전압 제어 발진기(Voltage controlled oscillator)
• 3.3.7 저강하형 선형 전압 레귤레이터(Low-dropout regulator)
• 3.3.8 더미 블록(Dummy block)
• 제 4 장 전체 회로 구현 및 시뮬레이션
• 4.1 전체 회로 구현
• 4.2 시뮬레이션 결과를 통한 동작 및 성능 확인
• 4.3 요약
• 제 5 장 결론