처리속도 향상과 면적 효율을 위한 VDC-M 디코더의 부분 병렬화 하드웨어 설계

다국어 초록 (Multilingual Abstract)

With the rapid growth in demand for high-resolution and high-refresh-rate mobile and embedded displays, it has become increasingly difficult to satisfy the bandwidth requirements of display interfaces using only the physical layer. To address this issue, VESA has standardized VDC-M (VESA Display Compression-M), a visually lossless display compression scheme for real-time panel interfaces. This thesis proposes a VDC-M decoder hardware architecture capable of real-time processing of Full HD (1920×1080) images.
In this work, three decoder architectures with different degrees of parallelism are designed and analyzed. These architectures include a fully-serial architecture that processes the three color components sequentially, a fully-parallel architecture that decodes all components simultaneously, and a partial-parallel architecture that selectively applies parallel processing according to the computational characteristics of each component.
The proposed partial-parallel VDC-M decoder is designed at the RTL level using Verilog HDL and synthesized using a 65 nm standard cell library. Synthesis results show that the proposed decoder occupies 700,758 gates and operates at a maximum frequency of 555 MHz, achieving a throughput of 77.1 Mpixels/s, which corresponds to approximately 37 frames per second for Full HD resolution.

목차 (Table of Contents)

• Ⅰ. 서 론 1
• 1.1 연구 배경 1
• 1.2 연구 방법 5
• Ⅱ. VDC-M 디코딩 이론 7
• 2.1 이미지 계층 구조 7
• 2.2 디코딩 과정 8
• 2.2.1 서브스트림 디멀티플렉서 10
• 2.2.2 레이트 제어 12
• 2.2.3 코딩 모드 14
• 2.2.3.1 Transform 모드 14
• 2.2.3.2 BP 모드와 BP-SKIP 모드 16
• 2.2.3.3 MPP 모드와 MPPF 모드 18
• 2.2.4 엔트로피 디코딩 20
• 2.2.5 색 공간 변환 23
• Ⅲ. 제안하는 부분 병렬 VDC-M 디코더 회로 구조 24
• 3.1 부분 병렬 VDC-M 디코더 회로 구조 26
• 3.1.1 서브스트림 디멀티플렉서 모듈 29
• 3.1.2 잔차 디코딩 모듈 31
• 3.1.3 예측 모듈 33
• 3.2 전체 직렬 VDC-M 디코더 회로 구조 35
• 3.3 전체 병렬 VDC-M 디코더 회로 구조 37
• Ⅳ. 실험 결과 39
• Ⅴ. 결 론 45
• 참 고 문 헌 47