VDC-M 표준 기반 고성능 인코더 회로 설계

다국어 초록 (Multilingual Abstract)

With the increasing resolution and refresh rate of modern displays, the transmission bandwidth required by display interfaces has grown rapidly. To support display systems that require low latency and real-time processing in such environments, VESA has introduced the VDC-M (VESA Display Compression-M) standard, which adopts an intra-frame compression scheme. However, due to its complex encoding structure, VDC-M poses significant challenges in hardware implementation, where processing latency and computational complexity become major design constraints. In particular, the test encoding mode, which evaluates multiple encoding modes for each block, is identified as a key bottleneck that limits the overall throughput of the encoder.
In this thesis, the VDC-M encoder algorithm is analyzed and restructured into a hardware architecture suitable for RTL-level implementation. Based on this analysis, a high-performance VDC-M encoder architecture capable of operating in both single-slice and multi-slice configurations is proposed. The proposed architecture reduces processing latency by narrowing the search range of the BP(Block Prediction) mode, which has the highest computational complexity in the test encoding mode, and by parallelizing the entropy coding process.
The proposed encoder is synthesized using a 65 nm standard cell library. In the single-slice configuration, the high-performance VDC-M encoder operates at a maximum frequency of 171 MHz with an area of approximately 3.8 M gates, achieving about 51 frames per second for FHD resolution. In the multi-slice configuration, the encoder operates at a maximum frequency of 164 MHz with an area of approximately 15.1 M gates, achieving about 195 frames per second for FHD resolution and about 49 frames per second for 4K resolution.

목차 (Table of Contents)

• Ⅰ. 서 론 1
• 1.1 연구 배경 1
• 1.2 연구 방법 5
• Ⅱ. VDC-M 인코더 이론 6
• 2.1 이미지 계층 구조 6
• 2.2 인코딩 과정 7
• 2.2.1 색 공간 변환 8
• 2.2.2 평탄도 검출 9
• 2.2.3 레이트 제어 11
• 2.2.4 테스트 인코딩 모드 13
• 2.2.4.1 Transform 모드 14
• 2.2.4.2 BP 모드 16
• 2.2.4.3 MPP 모드 18
• 2.2.4.4 MPPF 모드 20
• 2.2.4.5 BP-SKIP 모드 21
• 2.2.5 엔트로피 인코딩 22
• 2.2.6 서브스트림 멀티플렉서 24
• Ⅲ. 제안하는 VDC-M 인코더 회로 구조 26
• 3.1 단일 슬라이스 기반 기본 VDC-M 인코더 회로 구조 26
• 3.1.3 Transform 모듈 29
• 3.1.3.1 Intra 예측 모듈 31
• 3.1.4 BP 모듈 32
• 3.1.4.1 BP 탐색 모듈 34
• 3.1.5 MPP 모듈 35
• 3.1.6 모드 인코딩 모듈 36
• 3.1.7 서브스트림 멀티플렉서 모듈 37
• 3.2 단일 슬라이스 기반 고성능 VDC-M 인코더 회로 구조 39
• 3.3 멀티 슬라이스 기반 VDC-M 인코더 회로 구조 44
• Ⅳ. 실험 결과 45
• Ⅴ. 결 론 49
• 참 고 문 헌 50