Utilization of Internal-Node Loading Capacitance in Current-Latched Sense Amplifiers for High-VBL Offset Suppression

다국어 초록 (Multilingual Abstract)

We present an internal-node-loading capacitance current-latched sense amplifier (INC-CLSA) that suppresses the high bit-line voltage (VBL) offset dominated by latch-NMOS mismatch. By introducing a compact loading capacitance at the internal nodes, the input transistor pair remains in saturation region longer, reducing sensitivity to latch-pair threshold-voltage mismatch without increasing cell area. Fabricated in 28-nm CMOS, the INC-CLSA scheme achieves 32.7% offset reduction (and 46.8% with an internode precharge switch) over a conventional CLSA at VBL = 1.0 V, all within the same footprint. Post-layout simulations further show up to 59% offset reduction using stacking metal capacitors with minimal timing and energy penalties. The technique is layout-friendly and offers zero-footprint metal- based implementations, requires no additional control phases, and integrates seamlessly with existing sensing schemes, making it suitable for global-reference sensing and other high-speed SA applications.

목차 (Table of Contents)

• Abstact i
• Table of Contents ii
• List of Tables iii
• List of Figures iv
• Chapter 1. Introduction 1
• Chapter 2. VOS Analysis 3
• Chapter 3. Utilization of INC-CLSA 7
• Chapter 4. Post-Layout Validation and Layout Guideline 11
• 4.1. NMOSCAP 12
• 4.2. Metal CAP 12
• 4.3. Stacking Metal CAP 12
• 4.4. Dangling Metal CAP 13
• Chapter 5. Measurement Results 16
• Chapter 6. Conclusion 21
• Reference 22
• 국문초록 25
• 감사의 글 27
• iii