Parallel-to-Series Reconfigurable Switched-Capacitor based Equalizer with Enhanced Charge Transfer per Cycle

다국어 초록 (Multilingual Abstract)

Cells in series-connected lithium-ion battery packs inevitably become imbalanced over time due to manufacturing variations, temperature gradients, aging, and differences in self-discharge. This cell imbalance reduces usable pack capacity, shortens lifetime, and becomes especially problematic under fast-charging conditions, where the charge process must be terminated early to avoid overcharging the highest-voltage cell. Conventional direct cell-to-cell (DC2C) balancing circuits suffer from inherently slow operation because the charge transferred in each switching cycle is directly limited by the instantaneous voltage difference between cells, which becomes very small in the later stage of balancing. To overcome this limitation, this thesis proposes a parallel-to-series reconfigurable switched-capacitor equalizer. In the proposed architecture, multiple capacitors are charged in parallel and then discharged in series, which increases the effective transfer voltage and enhances the charge delivered to the low-voltage cell in each cycle. Analytical charge-sharing calculations are carried out to evaluate the charge transfer characteristics and the utilization of the balancing capacitors in the proposed circuit. A frequency-domain analysis is also performed to derive the equivalent resistance of the balancing network and to identify an appropriate switching frequency; based on the trade-off between equivalent resistance and transferred charge per cycle, an operating frequency of 100 Hz is selected. Based on 3.6 V, 2,800 mAh lithium-ion cells, both simulations and measurements were carried out to evaluate the proposed equalizer. The results show that, as the cell voltage difference decreases, the charge transferred per cycle in the conventional DC2C circuit approaches 0 C, whereas the proposed method maintains a charge transfer of about 1.29 mC per cycle. This behavior overcomes the inherent limitation of the conventional DC2C topology and significantly accelerates the balancing process. In addition, the proposed circuit requires only three extra switches regardless of the number of series-connected cells, resulting in minimal hardware overhead.

목차 (Table of Contents)

• Abstract ............................................................................................................................... i
• Table of Contents ................................................................................................................ ii
• List of Tables ..................................................................................................................... iv
• List of Figures ................................................................................................................... v
• Chapter 1. Introduction ....................................................................................................... 1
• 1.1. Background ................................................................................................................. 1
• 1.2. The Composition of a Paper ........................................................................................ 7
• Chapter 2. Basic of the Balancing ...................................................................................... 8
• 2.1. Passive Balancing ........................................................................................................ 8
• 2.2. Active Balancing ......................................................................................................... 9
• 2.2.1. Adjacent C2C ........................................................................................................... 9
• 2.2.2. Direct C2C .............................................................................................................. 10
• 2.2.3. Limitation of DC2C ................................................................................................ 10
• Chapter 3. Proposed Balancing Method ........................................................................... 12
• 3.1. Proposed Circuit ........................................................................................................ 12
• 3.2. Concept of the Proposed Balancing Method ............................................................. 14
• 3.3. Theoretical Analysis of Proposed DC2C circuit ........................................................ 15
• 3.4. Optimizing Parameters with Theoretical Analysis .................................................... 24
• Chapter 4. Result of Simulation and measurement........................................................... 34
• 4.1. Result of Simulation .................................................................................................. 34
• 4.2. Result of Measurment................................................................................................ 37
• Chapter 5. Conclusion ...................................................................................................... 43
• Bibliography ..................................................................................................................... 44
• 국문초록 .......................................................................................................................... 48