Multiple Node Upset Tolerant and Self-Recoverable Latch Designs for Aerospace Applications

다국어 초록 (Multilingual Abstract)

Due to the continuous scaling down of transistor size in integrated circuits, sensitive nodes are becoming increasingly vulnerable to node upset, especially in aerospace, because of their high radiation environment. This paper presents a low- cost double-node-upset (DNU) fully-tolerant and triple-node-upset (TNU) partially- tolerant self-recoverable latch (DFTPRL) design utilizing a high transmission path and clock-gating technique, and a recovery-signal based low-cost quadruple node upset (QNU) tolerant and self-recoverable latch (RS-QNURL) design with inclusion of high transmission switch. The proposed latch design DFTRL provides high stability and rapid response against DNU, while also maximizing TNU tolerance by incorporating a maximum number of logic stages between nodes for self-recovery. The RS-QNURL latch further achieves complete QNU self-recovery through the incorporation of a recovery-signal-based mechanism, eliminating the need for any layout-dependent techniques for recovery process. Post-layout HSPICE simulation results using 28 nm model parameters clearly show the reliability of these proposed designs.

목차 (Table of Contents)

• Abstract i
• Table of Contents ii
• List of Table v
• List of Figure vi
• List of Nomenclature ix
• Chapter1. Introduction 1
• 1.1. Research Background and Motivation 1
• 1.2. Impact of Soft Error with Technology Scaling 2
• 1.3. Research Purpose 3
• 1.4. Dissertation Organization 4
• Chapter 2. Existing Latch Design with Limitations 5
• 2.1. Existing Mitigation Techniques 5
• 2.2. Contemporary Radiation-Hardened Latch Designs and Their Drawbacks 6
• Chapter 3. Proposed DFTPRL Designs 9
• 3.1. Schematic of Proposed DFTPRL Latch 9
• 3.2. Operational Behavior of Proposed DFTPRL Latch 12
• 3.3. Noise Propagation Logic Stage (NPLS) 13
• 3.4. Self-Recovery Analysis of DFTPRL Latch 15
• 3.4.1. DNU Self-Recoverability 16
• 3.4.2. TNU Self-Recoverability 20
• 3.5. Simulation Conditions for Proposed DFTPRL Latch 24
• 3.5.1. DNU Simulation Results 25
• 3.5.2. TNU Simulation Results 27
• 3.6. Performance Analysis with PVT Variations of DFTPRL Latch 33
• 3.7. Comparative Analysis with Existing Latches Based on Simulation Results 38
• 3.7.1. Comparison Analysis Based on Peak Current with DRLW 41
• 3.7.2. Comparison Analysis Based on Noise Length with DRLW 42
• 3.7.3. Comparison Analysis Based on Size of Transistors with DRLW 43
• 3.7.4. Comparison with Existing Latches 45
• Chapter 4. Proposed RS-QNURL Designs 49
• 4.1. Schematic of Proposed RS-QNURL Latch 49
• 4.2. Functional Behavior of Proposed RS-QNURL Latch 52
• 4.3. Self-Recoverability Analysis of RS-QNURL Latch 53
• 4.3.1. QNU across the Same SEI SRAM Cell 54
• 4.3.2. QNU across the CE Tree 56
• 4.3.3. QNU across SEI SRAM Cells and CE Tree 58
• 4.4. REC Signal 62
• 4.5. Simulation Result Analysis of Proposed RS-QNURL Latch 63
• 4.6. Performance Analysis with PVT Variations of RS-QNURL Latch 69
• 4.7. Comparative Analysis with Existing Latches Based on Simulation Results 72
• 4.7.1. Comparison Analysis Based on Self-Recoverability with LC- QNUTL 73
• 4.7.2. Comparison with Existing Latches 77
• Chapter 5. Conclusion 80
• Reference 81
• 국문 초록 87