Monolithic 3D (M3D) integration technology offers a path to ultra-high resolution, low latency, and energy-efficient circuits required for interactive VR/AR displays. This study demonstrates the implementation of M3D complementary logic by vertically ...
Monolithic 3D (M3D) integration technology offers a path to ultra-high resolution, low latency, and energy-efficient circuits required for interactive VR/AR displays. This study demonstrates the implementation of M3D complementary logic by vertically integrating hysteresis-free p-type top-gated single-walled carbon nanotube (SWNT) field-effect transistors (FETs) and n-type metal-oxide FETs (NMOSFETs). Hysteresis suppression is achieved through spin-on glass (SOG) and HfO₂ encapsulation, enabling stable and reliable SWNT operation. The resulting CMOS inverters exhibit low power consumption, high reliability, and reduced photocurrent due to the top-gated structure critical for high-resolution active-matrix display backplanes. The feasibility of this approach is validated by directly driving red and blue micro-LEDs with the complementary inverter scheme within a 5 V supply, confirming full pixel-level functionality through monolithic integration. This scalable M3D strategy meets stringent power and pixel-density requirements, advancing heterogeneous channel material integration for next-generation AR/VR display technologies.