High-k Capping Layer Effects on Reliability of SWNT Field Effect Transistors with Spin-On-Glass Buffer Layer = 스핀-온-글라스 버퍼층을 갖는 단일벽 탄소나노튜브 전계 효과 트랜지스터의 신뢰성에 대한 고유전율 캡핑층 효과

다국어 초록 (Multilingual Abstract)

The rapid growth of augmented reality (AR) and virtual reality (VR) applications has accelerated the demand for high-resolution and low-power display technologies. Micro-light-emitting diodes (Micro-LEDs) are regarded as a promising solution; however, their implementation requires high-performance thin- film transistors (TFTs) capable of delivering sufficient drive current under compact and low-temperature process conditions. Conventional a-Si and LTPS TFTs exhibit intrinsic limitations under such requirements. In this context, single-walled carbon- nanotube (SWNT)-based field-effect transistors (FETs) have emerged as attractive candidates for next-generation display drivers owing to their high mobility, mechanical flexibility, and low-temperature process compatibility. Nevertheless, gate-field-induced hysteresis—particularly charge trapping associated with hydroxyl (–OH) groups—remains a major technical challenge. To overcome this issue, this study introduces a dual-stack gate-dielectric structure employing a Spin-on-Glass (SOG) buffer and a high-κ oxide layer. Electrical performance and reliability were systematically evaluated through dual- gate operation, pulsed-bias measurements, and low-frequency noise (LFN) analysis. The hysteresis and bias-stress instabilities were found to be governed by interface- trap dynamics, where Al₂O₃ introduces shallow fast traps, HfO₂ exhibits moderate trap activity, and ZrO₂ forms deep slow traps that affect long-term stability. The HfO₂-capped device exhibited a negligible hysteresis of ~0.1 V, while the ZrO₂-based transistor achieved the highest field-effect mobility (≈ 35 cm² V⁻¹ s⁻¹) and the lowest contact resistance. Under ±3 V gate stress, electron trapping was dominant (ΔVTH ≈ 0.6–0.9 V), whereas hole trapping was effectively suppressed due to the large injection barrier (≈ 2.5–3.4 eV). The normalized noise spectra followed the carrier- number-fluctuation model, and the extracted trap-density trend was Al₂O₃ > HfO₂ > ZrO₂. The proposed SWNT FETs were further applied to various logic circuits. Inverter, NAND, and NOR gates demonstrated stable switching behavior, and the bootstrap-capacitor inverter achieved a high voltage gain of ~4.3 at VDD = 4 V. Furthermore, Micro-LED driving using the fabricated SWNT FETs and inverters enabled precise analog control and stable AC on/off modulation of RGB μ-LEDs. In conclusion, this study demonstrates that the SOG/High-k based SWNT FET platform, fabricated entirely below 250 °C, offers excellent process compatibility with monolithic 3D (M3D) and system-in-package (SiP) architectures, confirming its strong potential for scalable, low-power integration in next-generation display driver circuits and flexible logic systems.

목차 (Table of Contents)

• Abstract i
• Table of Contents iii
• List of Tables v
• List of Figures vi
• Chapter 1 Introduction 1
• 1.1 Research Background 1
• 1.2 Limitations of Conventional SWNT FETs 3
• 1.3 Necessity of the SOG Buffer Layer 5
• 1.4 Necessity of Dual-Gate Architecture in Display Application 10
• Chapter 2 Experimental Details 12
• 2.1 Device Fabrication Process 12
• 2.2 Electric Measurements 14
• Chapter 3 Results and Discussion 16
• 3.1 Electrical Characteristics 16
• 3.2 Dual-Gate Coupling and Electrostatic of SOG/High-k SWNT FETs 23
• 3.3 Trap Characterization of SOG/High-k SWNT FETs 30
• Chapter 4 Application 44
• 4.1 Logic gates of SOG/HfO2 SWNT FETs 44
• 4.2 μ-LED Driving of SOG/HfO2 SWNT FETs 47
• Chapter 5 Conclusion 49
• Summary 52
• References 53
• 국문초록 58
• Acknowledgements 61
• Curriculum Vitae 63