Equalization Techniques for Single-Ended PAM-3 Transceivers in High-Speed Memory Interfaces

다국어 초록 (Multilingual Abstract)

In memory interfaces, data rates continue to increase. However, channel loss attenuates and distorts high-speed data, which degrades signal integrity. To address these issues, pulse-amplitude modulation (PAM) has been adopted in memory interfaces as an alternative to non-return-to-zero (NRZ) signaling. Three-level pulseamplitude modulation (PAM-3) provides 1.5 times higher bit efficiency than NRZ and 1.5 times larger voltage margin than four-level pulse-amplitude modulation (PAM-4), offering a balanced trade-off between bandwidth efficiency and voltagemargin. However, PAM signaling still suffers from reduced voltage margin and increased circuit complexity, which increases power consumption and makes it more susceptible to inter-symbol interference (ISI). Therefore, advanced transceiver (TRX) architectures are required to ensure high-speed and low-power operation. This paper proposes transmitter (TX) and receiver (RX) architectures for a single-ended PAM-3 transceiver. Conventional feed-forward equalizer (FFE) designs increase the load capacitance of the output driver, which degrades bandwidth and energy efficiency. To address this, the proposed TX adopts a switched-capacitor peaking (SCP) TX that minimizes driver loading while simplifying the equalizer structure. Conventional single-ended PAM-3 receivers require single-to-differential converters (S2Ds) and reference voltage generators, which increase power consumption and circuit complexity. The proposed RX employs a summer-merged transimpedance amplifier (SMTIA) that merges decision-feedback equalization (DFE) into the TIA, thereby removing the need for S2D and reference generation. As a result, both power consumption and area overhead are reduced. In addition, an active inductor provides high-frequency boosting, effectively mitigating ISI caused by channel loss. Simulation results of the proposed TX, implemented in a 28-nm CMOS process, show -9.2 dB channel loss compensation at 8 GHz with an energy efficiency of 0.127 pJ/b/dB, achieving a vertical eye margin of 61 mV and a horizontal margin of 0.65 UI. The proposed RX achieves 24 Gb/s operation under -6.55 dB channel attenuation with an energy efficiency of 0.39 pJ/b, providing a vertical eye margin of 204 mV and a horizontal margin of 0.69 UI.

목차 (Table of Contents)

• Abstract ...................................................................................................................i
• Table of Contents ...................................................................................................ii
• List of Tables........................................................................................................ iii
• List of Figures.......................................................................................................iv
• Chapter 1. Introduction ..........................................................................................1
• 1.1. Background of Study ............................................................................1
• 1.2. The Composition of a Paper..................................................................3
• Chapter 2. Single-Ended PAM-3 Transmitters.......................................................4
• 2.1. Conventional Single-Ended Transmitters .............................................4
• 2.2. Insertion Loss........................................................................................5
• 2.3. Feed-Forward Equalizer........................................................................6
• 2.3.1 Discrete taps feed-forward equalizer ..........................................8
• 2.3.2 Capacitor peaking feed-forward equalizer................................10
• 2.3.3 Pulse width modulation feed-forward equalizer .......................12
• 2.4. Implementation of the Proposed Transmitter......................................13
• 2.4.1 Transition of three-level pulse amplitude modulation ..............14
• 2.4.2 Operation of proposed switched capacitor peaking ..................20
• 2.5. Simulation Results of Proposed TX....................................................22
• Chapter 3. Single-Ended PAM-3 Receivers.........................................................25
• 3.1. Conventional Single-Ended Receiver.................................................25
• 3.2. Proposed Single-Ended PAM-3 Receiver .........................................32
• 3.3. Simulation Results of Proposed RX ..................................................42
• Chapter 4. Conclusion..........................................................................................46
• References............................................................................................................47
• 국문초록..............................................................................................................52