Design of Low-Power PAM-4 Transmitter with Charge-Steering Feed-Forward Equalizer for Memory Interfaces = 메모리 인터페이스를 위한 전하 구동 등화기를 활용하는 저전력 PAM-4 송신기 설계

다국어 초록 (Multilingual Abstract)

As the demand for high-bandwidth memory increases, the per-pin data rate of serial links must increase by a factor of two to three every two years. To support such bandwidths with reasonable power consumption, an overall transmitter efficiency of approximately 1 mW/Gb/s is required. Current-steering circuits operate at high speed but draw significant static power, whereas rail-to-rail CMOS circuits avoid static bias but at the cost of speed. This work presents the development of a low-power 16-Gb/s PAM-4 transmitter with feed-forward equalizer, which is implemented using a charge-steering paradigm and additional circuit techniques. Compared with prior works, the proposed feed- forward equalizer achieves more than a three-fold reduction in power consumption. Fabricated in a 28-nm CMOS technology, the design occupies an active area of 0.016 mm2. An experimental prototype consumes 13.81 mW from a 1-V supply and achieves the energy efficiency of 0.86 pJ/bit/pin at 16 Gb/s/pin.

목차 (Table of Contents)

• Abstact i
• Table of Contents ii
• List of Tables iii
• List of Figures iv
• Chapter 1. Introduction 1
• 1.1. Movitation 1
• 1.2. Thesis oragnization 1
• Chapter 2. Theorical background 3
• 2.1. Basic of multi-level signaling 3
• 2.2. Conventional PAM-4 driver 7
• 2.2.1. Source-series termination driver 7
• 2.2.2. Current-mode logic driver 9
• Chapter 3. Charge-steering based equalization architecture 10
• 3.1. Concept 11
• 3.2. Design of charge-steering feed-forward equalizer 13
• 3.3 Extension to PAM-4 signaling 23
• Chapter 4. Low-power PAM-4 transmitter 31
• 4.1. Output driver 32
• 4.2. Encoder 35
• Chapter 5. Experimental results 37
• Chapter 6. Conclusion 41
• References 42
• 국문초록 45