Area-Efficient/Low-Power MRAM-PIM based on Crossbar Array utilizing Ternary Output

다국어 초록 (Multilingual Abstract)

Most recent artificial intelligence services are implemented using deep learning–based artificial neural networks. These networks are powerful tools for learning meaningful representations from unstructured data, and in recent years a variety of architectures have converged and become standardized around convolutional neural networks. As such neural-network models grow in complexity and are deployed more widely, their computational workload and energy consumption increase dramatically, highlighting the need for high-performance, low-power hardware accelerators that can handle these workloads efficiently. In this thesis, an MRAM-based analog process-in-memory (MPIM) architecture with ternary neuron outputs is proposed. The proposed architecture (1) improves array efficiency by binarizing inputs to {0, 1} instead of {−1, 1}, (2) mitigates accuracy degradation through an input-dependent current compensation circuit, and (3) reduces conversion energy overhead via a 3-bit down-scaling ADC. Simulation results using a two-layer perceptron show that the proposed MPIM achieves 90.3% inference accuracy on the MNIST dataset and a peak energy efficiency of 819.8 TOPS/W at 200 MHz.

목차 (Table of Contents)

• Abstact i
• Table of Contents ii
• List of Tables iii
• List of Figures iv
• Chapter 1. Introduction 1
• Chapter 2. Preliminaries 3
• 2.1. MTJ Resistance States 3
• 2.2. MAC Operation in Crossbar Array 4
• 2.3. Previous MRAM Bit-Cell 6
• Chapter 3. Proposed MPIM Architecture 9
• 3.1. 2T-2MTJ Bit-Cell with Ternary Output 9
• 3.2. Current Compensation Circuit for High Accuracy 13
• 3.3. Down Scaling ADC 17
• 3.4. Sub/Add for Total Sum 20
• 3.5. Overall Architecture 22
• Chapter 4. Simulation 24
• 4.1. Simulation Conditions 24
• 4.2. Circuit Level Results 25
• 4.3. System Level Results 27
• Chapter 5. Comparison 29
• Chapter 6. Conclusion 31
• Reference 32
• 국문초록 36
• 감사의 글 38