CMOS 65nm 공정의 정확한 dB-linear 특성을 위한 광대역 기저대역 가변이득 증폭기 설계 : Design of a Wideband Variable GainAmplifier for Accurate dB-Linear Characteristic in 65nm CMOS Technology = Design of a Wideband Variable Gain Amplifier for Accurate dB-Linear Characteristic in 65nm CMOS Technology

다국어 초록 (Multilingual Abstract)

Design of a Wideband Variable Gain Amplifier fo Accurate dB-Linear Characteristic in 65nm CMOS Technology Assyifa Nur Annisa Rizkia Putri Dept. of Electronics Engineering Graduate School Hanbat National University Advisor : Youngwoo Ji This work presents a dB-linear Variable Gain Amplifier (VGA) based on an active-RC feedback filter topology, employing a ramp-based control scheme with an integrator feedback loop for DC offset cancellation. The VGA incorporates a power-efficient feed-forward compensated Operational Transconductance Amplifier (OTA) achieving a unity-gain bandwidth of 8.64 GHz, 35.81 dB gain, and 43.57° phase margin while consuming 3.15 mW. Fabricated in 65 nm CMOS technology, the proposed VGA demonstrates a high linearity with 21.52 dBm OIP3 and operates over a wide passband from 9.9 kHz to 683 MHz. It offers a 30 dB-linear gain tuning range with 0.4 dB gain error, 51 dB DC offset attenuation, and a cancellation range from ±0.0015 mV. The design consumes 19.5 mW from a 1.2 V supply and occupies 0.42 mm² active area. Index terms: automatic gain control (AGC), dB-linear, feedforward compensation, operational transconductance amplifier (OTA), ramp-controlled, RC-feedback topology, variable gain amplifier (VGA).

목차 (Table of Contents)

• List of Table ⅰ
• List of Figures ⅱ
• Abstract ⅳ
• 1. Introduction 1
• 1.1. Motivation 2
• 1.2. Objectives and Thesis Overview 4
• 2. Realization of dB-Linear VGA 6
• 2.1. Previous Works 6
• 2.2. Variable Control Scheme with active-RC Filter Structure 10
• 3. A dB-Linear VGA based on Active-RC Feedback Topology with a Ramp-based
• Control Scheme with an Integrator Feedback Loop as DC Offset Cancellation 14
• 3.1. Proposed FF Compensation 15
• 3.2. VGA System Architecture 22
• 3.3. DC Offset Cancellation Feedback Network 24
• 3.4. Circuit Design 28
• 3.5. Layout of The Proposed Design 30
• 4. Simulation Results and Comparison 31
• 4.1. Post-layout Simulation Results 31
• 4.2. Comparison 34
• 5. Conclusions 36
• References 37
• 국 문 요 약 42
• Acknowledgement 43