Signal Integrity (SI) Degradation Analysis for Command/Address in Memory Interfaces with Branch Topology and SI Improvement Methods = 고속 메모리 인터페이스의 분기구조에서 발생하는명령/주소 신호의 신호 무결성 열화 분석 및 개선 방법 제안

다국어 초록 (Multilingual Abstract)

This paper presents mitigation techniques to address signal-integrity degradation caused
by branch topologies in high-speed memory interfaces. The study examines the use of
damping resistors with optimized connections and adjustments to trace width within a
single net to better control characteristic impedance. Branch topology induced
discontinuities were modeled and analyzed, and the effectiveness of the proposed
methods was evaluated through eye diagrams, S-parameter. The analysis shows that the
original channel struggled to meet eye-mask requirements because of reflections and
impedance mismatches from the branching topology. An analysis of signal integrity
with respect to the placement of the meander was also performed. In contrast, the
proposed mitigation methods significantly improved signal integrity, restoring
sufficient eye-mask margin and effectively reducing the adverse impact of branching induced discontinuities. The proposed approaches provide practical and implementable
design guidelines for addressing SI degradation in memory interfaces. These findings
offer valuable insights for future high-speed memory interface design and contribute to
the development of more robust and reliable next-generation memory systems.

목차 (Table of Contents)

• Abstract i
• Contents ii
• List of Figures iv
• List of Tables vi
• Chapter 1 Introduction 1
• 1.1 Backgrounds 1
• 1.2 Thesis Organization 8
• 1.3 Necessity of Research 10
• Chapter 2 Analysis of Command/Address (CA) Signal Integrity Degradation
• Caused by Branch Topology based on CA Channel Modeling 12
• 2.1 The Causes of Signal integrity Degradation in Branch Topology 12
• 2.2 Simulation Set up for Degradation Implementation 18
• 2.3 Analysis of Branch Topology Simulations 25
• Chapter 3 Mitigation of Signal Integrity Degradation in CA Channels based on a
• Damping Resistor and Meander Design Modifications 29
• 3.1 Method of Damping Resistor 29
• 3.2 Method of Adjustment Characteristic Impedance 39
• 3.3 Analysis of Signal Integrity Effects Due to Meander Line Location and Design
• Guidelines 44
• Chapter 4 Application of the Proposed Methods to the Memory Interface with
• Branch Topology in the Next Generation Board 49
• 4.1 Analysis of Signal Integrity Degradation Caused by Branch Topology in Practical
• Operating Environments 49
• 4.2 Analysis of Improved Simulation-Based Signal Integrity Achieved Through the
• Proposed Induced Methods 59
• Chapter 5 Conclusion 65
• Bibliography 68
• 국문초록70