This dissertation thoroughly investigates ferro-resistive switching (FRS) behavior in metal-ferroelectric-dielectric-metal (MFDM) tunnel junctions to advance their use as scalable and reliable non-volatile memory devices.
The study confirms that in as...
This dissertation thoroughly investigates ferro-resistive switching (FRS) behavior in metal-ferroelectric-dielectric-metal (MFDM) tunnel junctions to advance their use as scalable and reliable non-volatile memory devices.
The study confirms that in asymmetric MFDM configurations, FRS behavior stems from ferroelectric polarization switching, validated by nucleation-limited-switching (NLS) analysis and one-dimensional (1-D) dynamic tunneling simulations. It highlights the crucial role of the interfacial dielectric layer, which facilitates charge injection, modulates electrostatic potential, and acts as a tunneling barrier.
A comparative study of ferroelectric Hf0.5Zr0.5O2 (HZO) and Al0.7Sc0.3N (ASN) reveals ASN's superior FRS performance in current density and read stability. This is attributed to its lower barrier height and higher coercive field. ASN-based devices showed higher ON currents and improved read disturbance immunity, particularly in asymmetric MFDM structures, demonstrating the benefit of wide read voltage windows enabled by ASN's intrinsic properties.
To further optimize FRS characteristics, interfacial dielectric engineering was applied to ASN-based ferroelectric tunnel junctions (FTJs). Electrical and simulation analyses showed that dielectric (DE) layers with moderate barrier heights, such as HfO2 and ZrO2, enable efficient ON-state conduction while suppressing OFF-state leakage. The ZrO2/ASN system achieved the highest ON/OFF ratio and most stable retention, proving its potential for robust non-volatile memory.
The collective findings of this dissertation underscore the superiority of ASN as a ferroelectric material for MFDM tunnel junctions, alongside the optimization of the interfacial dielectric layer. The insights derived from this work provide a framework for the design of bilayer tunnel junctions, thereby supporting the development of high-performance, CMOS-compatible non-volatile memory technologies.