Structural Modification for Enhancing the Electrical Performance of IGZO Thin-Film Transistors = 구조적 변형을 통한 IGZO 트랜지스터의 전기적 성능 향상

다국어 초록 (Multilingual Abstract)

The advancement of next-generation technologies such as high-resolution displays, AR/VR, and high-density memory demands both high performance and increased integration of thin-film transistors (TFTs). In this context, amorphous IGZO has emerged as a promising channel material due to its compatibility with low-temperature processes, excellent uniformity, and low leakage current characteristics. However, continuous scaling in both channel length and thickness has introduced critical bottlenecks in IGZO TFTs, including degradation in field-effect mobility, exacerbation of short-channel effects (SCE), and a sharp increase in contact resistance in ultra-thin channels. To fundamentally address these scaling-induced challenges, this dissertation proposes an integrated approach that combines structural design and interfacial engineering. The strategy is systematically analyzed across three core directions: First, to suppress short-channel effects, a stepped substrate was introduced into a self-aligned coplanar (SAC) structure. This design utilizes vertical steps in the underlying dielectric to extend the gate dielectric coverage beneath the channel, effectively suppressing lateral carrier diffusion from the source/drain regions. TLM and TEM analyses verified that this structure maintains stable threshold voltage behavior even when the channel length is scaled down to 2 µm. Second, to mitigate the increase in contact resistance in ultra-thin IGZO channels, an ALD-grown Al2O3 interlayer was inserted at the metal/IGZO interface. This interfacial layer effectively suppressed the reduction reaction induced by Ti metal, thereby improving interface alignment and charge injection properties. The optimized interlayer maintained excellent interfacial characteristics while remaining compatible with post-fabrication processes, enabling stable device operation without Rc degradation under aggressive scaling conditions. Third, to counteract the inevitable mobility degradation associated with scaling, a geometry-based design strategy for the metal capping layer (MCL) was introduced. This approach leverages precise control over the spatial distribution of metal diffusion boundaries to preserve mobility margins. Various MCL structures were fabricated with identical metal coverage but different gap, width, and length configurations. The results demonstrated that higher diffusion boundary density led to an expansion of the electrostatically active region and the formation of quasi-continuous conductive paths, resulting in significant mobility enhancement, as confirmed by KPFM and TCAD simulations. Overall, this dissertation explores the interplay between structural geometry, interfacial chemistry, and device architecture to overcome the limitations of oxide semiconductors. Through comprehensive investigations at both the thin film and device levels, it emphasizes the potential of structural design strategies in realizing high-performance oxide semiconductor TFTs.

국문 초록 (Abstract)

차세대 디스플레이, AR/VR, 고집적 메모리 기술의 발전은 박막 트랜지스터(TFTs)의 고성능화 및 고집적화를 요구하고 있으며, 이에 따라 비정질 IGZO은 저온 공정 호환성, 높은 균일성, 낮은 누설 전류 특성으로 인해 유력한 채널 재료로 주목받고 있다. 그러나 채널 길이와 두께의 지속적인 축소에 따라 IGZO TFTs는 전계 효과 이동도의 저하, 단채널 효과의 심화, 그리고 초박형 채널에서의 급격한 접촉 저항증가라는 병목 현상에 직면하게 된다. 본 논문에서는 이러한 스케일링 유도 병목을 근본적으로 해결하기 위해 구조 설계 및 계면 공정 기반의 통합적 접근을 제안하고, 이를 세 가지 핵심 전략으로 나누어 체계적으로 분석하였다. 첫째, 단채널 효과 억제를 위해 스스로 정렬된 공동평면 구조에 계단형 기판을 도입하였다. 이 구조는 채널 하부의 절연체 단차를 이용해 게이트 절연층의 피복 범위를 확장시켜, 소스/드레인 영역에서의 횡방향 캐리어 확산을 억제하고, 채널 길이가 2 µm까지 축소되더라도 문턱 전압 특성을 안정적으로 유지할 수 있음을 TLM 및 TEM 분석을 통해 검증하였다. 둘째, 초박형 IGZO 채널에서의 접촉 저항 문제를 완화하기 위해 금속/IGZO 계면에 ALD 기반 Al₂O₃ 중간층을 삽입하였다. 이를 통해 Ti 금속에 의한 계면 환원 반응을 억제하고, 계면 정렬 및 전하 주입 특성을 개선함으로써 접촉 안정성을 확보하였다. 최적화된 삽입층은 후공정 호환성과 함께 우수한 계면 특성을 유지하며, 스케일링된 구조에서도 컨택저항 증가 없이 안정한 동작을 가능하게 하였다. 셋째, 스케일링에 따라 불가피하게 발생하는 이동도 저하에 대응하기 위해, 금속 캡핑층의 기하학적 설계 전략을 도입하였다. 이는 금속 확산 경계의 공간적 분포를 정밀하게 제어할 수 있는 구조 설계를 통해 이동도 마진을 확보하는 새로운 전략을 제시하였다. 동일한 금속 피복 면적을 유지한 채, 금속 분포의 간격, 폭, 길이 등을 다르게 설계한 여러 구조를 비교한 결과, 확산 경계 밀도가 높은 설계일수록 정전기적으로 활성화된 영역이 확장되며, 준연속적인 전도 경로 형성을 통해 유의미한 이동도 향상이 나타남을 KPFM 및 TCAD 분석을 통해 입증하였다. 본 논문은 산화물 반도체의 한계점을 해소하기 위해 구조적 기하, 계면 화학, 소자 아키텍처의 상호작용을 분석하고, 박막 및 소자 수준의 체계적 연구를 통해 고성능 산화물 반도체 소자를 구현할 구조적 설계 전략의 잠재력을 강조한다.

목차 (Table of Contents)

• Abstract i
• Contents iv
• List of Tables ix
• List of Figures ix
• Chapter 1 Introduction 1
• 1.1 Material Properties and Scaling Challenges of IGZO Thin-Film Transistors 1
• 1.2 Dissertation Contributions and Organization 6
• Chapter 2 Suppressing Short Channel Effects Via a Stepped SiO2 Substrate 8
• 2.1 Research Background 9
• 2.2 Experiment 10
• 2.3 Electrical Characteristics of SAC-PL and SAC-SS TFTs 11
• 2.4 Comparative analysis of step height effect 13
• 2.5 Transmission Line Method (TLM) Analysis 16
• 2.6 Capacitance-Voltage (C-V) analysis 18
• 2.7 Technology Computer-Aided Design (TCAD) Simulation 20
• 2.8 Reliability: Subthreshold Swing and Bias Stress Tests 22
• 2.9 Process challenges and Industry feasibility 24
• 2.10 Summary 26
• Chapter 3 Contact Interface Engineering for Ultra-Thin IGZO channels Using ALD Al2O3 Interlayer 27
• 3.1 Research Background 28
• 3.2 Experimental 31
• 3.2.1 Device Fabrication 31
• 3.2.2 Characterizations 32
• 3.3 Thickness-Dependent Electrical Characteristics 33
• 3.4 Intrinsic Channel Integrity: Carrier Concentration, Morphology, Trap States, and Quantum‑Confinement Effects 35
• 3.4.1 Thickness-invariant Donor Concentration (ND) 35
• 3.4.2 Thickness‑Invariant IGZO Film Morphology 36
• 3.4.3 Bulk Trap Density Versus IGZO Thickness Bulk Trap Density Versus IGZO Thickness 36
• 3.4.4 Bandgap Enlargement and Quantum-Confinement Effects 39
• 3.5 Extrinsic Contact Characteristics: Interface Degradation, Contact-Limited Transport, Ohmic–Schottky Transition, SBH & TLM and STEM-EDS Analyses 42
• 3.5.1 Transfer Characteristics and Ohmic-to-Schottky Transition 42
• 3.5.2 TLM Analysis as a function of IGZO Thickness 46
• 3.5.3 Schottky Barrier Height Analysis versus IGZO Thickness 47
• 3.5.4 STEM–EDS Verification of Interfacial Redox Reactions 51
• 3.6 Contact Interface Engineering Strategy for Suppressing Degradation of Contact Properties 55
• 3.7 Electrical Properties of Ultra-thin 3 nm IGZO TFTs with Al₂O₃ Interlayer 56
• 3.7.1 Intrinsic Channel Integrity following Al₂O₃ Interlayer Deposition 58
• 3.7.2 Suppression of Contact Degradation via Al₂O₃ Interlayer Integration 60
• 3.7.3 STEM‑EDS Interface Analysis for Interfacial Stability 62
• 3.7.4 Influence of Al₂O₃ Interlayer Thickness on Interface Protection 63
• 3.7.5 Assessment of DIBL and Thermal Stability 66
• 3.8 Consideration and Industry feasibility 68
• 3.9 Summary 70
• Chapter 4 Mobility Enhancement Through Aluminum-Based Metal Capping Layer 72
• 4.1 Research Background 73
• 4.2 Experiment 74
• 4.2.1 Device Fabrication 74
• 4.2.2 Characterizations 75
• 4.3 Structural Design of Aluminum-Based Metal Capping Layer 76
• 4.4 Static Electrical Properties: Transfer and Output Characteristics 78
• 4.5 Fundamental Mechanisms Responsible for Mobility Enhancement 79
• 4.5.1 Electron‑Transfer Hypothesis Validated by KPFM 79
• 4.5.2 Depth-Profile XPS: Interfacial Redox Analysis 82
• 4.5.3 Peak-Deconvolution XPS: Quantifying Oxygen Vacancies 84
• 4.6 Structural dependence of mobility with Al-MCL configurations 86
• 4.6.1 TCAD Insight into Al Geometry: Length versus Width 88
• 4.6.2 Lateral Diffusion Profiling via KPFM 91
• 4.6.3 Gate-Dependent Contact Resistance Extracted by the Y-Function Method 93
• 4.7 Drain-Induced Vth offset Trade-off under Aggressive Al–S/D Engineering 97
• 4.8 Periodic-Island Al-PIA Architecture: Elucidating Lateral Diffusion Pathways 99
• 4.8.1 Design Principles and Geometric Optimization of Al-PIA 99
• 4.8.2 Al-PIA Gap Engineering for Quantitative Diffusion Validation 101
• 4.9 Verification of Edge-Induced Diffusion Overlap via KPFM Analysis 104
• 4.10 Reliability Evaluation under PBS/NBS Stress Conditions 108
• 4.11 Geometry-Driven Design Guidelines for Maximising Mobility in Al-MCL-Engineered IGZO TFTs 111
• 4.12 Consideration and Industry feasibility 113
• 4.13 Summary 114
• Chapter 5 116
• Bibliography 119
• 초록 127