(A) study on low power BLE advertising transmitter for tag IC applications

다국어 초록 (Multilingual Abstract)

This paper proposes a low-power Gaussian frequency-shift keying (GFSK)
transmitter for Bluetooth low energy (BLE) advertising. The proposed
transmitter is composed of an analog phase-locked loop (PLL) that performs
open-loop modulation and a power amplifier, which are optimized for the BLE
advertising mode, where the transmitter turns on for a short period of time to
transmit data and then turns off.
The analog PLL that performs open-loop modulation first generates the
target frequency output from a voltage-controlled oscillator (VCO) in a
closed-loop mode with negative feedback. The control voltage of the VCO at
this time is stored in a capacitor and input to the VCO through a buffer in the
subsequent open-loop mode. The output frequency offset caused by the
control voltage offset, which can be caused by the offset of the buffer, the
clock feed-through of the switch, etc., is measured using a counter and
compensated using the modulation capacitor bank of the VCO. No additional
circuitry is used to detect and compensate for the frequency offset, so the
area does not increase and the power consumption is reduced by the amount
of power consumed by the divider, phase-frequency detector, and charge
pump that operated for negative feedback.
The proposed power amplifier is implemented to ensure distortion-free spectrum radiation mask performance by smoothly increasing the output
power from the minimum power to the maximum power after it starts
operating, so that there is no sudden change in the output power.
The proposed analog PLL that performs open-loop modulation consumes
600 µA less current than closed-loop modulation, consumes 1.1 mW of power
at a supply voltage of 0.8 V, and the power amplifier consumes 4.9 mW of
power. The chip area is 1.17 mm² and the 55 nm CMOS process is used. The
measurement results confirmed that the offset occurring in open-loop
modulation is compensated.

국문 초록 (Abstract)

본 논문은 태그 IC용 Bluetooth low energy (BLE) advertising을 위한 저전력
Gaussian frequency-shift keying (GFSK) 송신기를 제안한다. 제안하는
송신기는 일정한 시간마다 켜진 후 짧은 시간 동안 데이터를 송신하고 다시 꺼지는
BLE advertising 방식에 특화되어 전력 소모를 최소화할 수 있는 열린 루프
변조를 수행하는 아날로그 위상동기루프와 구동증폭기로 구성되어 있다.
열린 루프 변조를 수행하는 아날로그 위상동기루프는 먼저 부정 피드백을
사용하는 닫힌 루프 모드에서 전압 제어 발진기로 목표 주파수의 출력을 생성하고
이때의 전압 제어 발진기의 제어 전압은 커패시터에 저장되어 이어지는 열린 루프
모드에서 버퍼를 통해 전압 제어 발진기에 입력된다. 버퍼의 오프셋, 스위치의
clock feed-through 등으로 발생할 수 있는 제어 전압 오프셋으로 인한 출력
주파수 오프셋은 카운터를 사용하여 측정되고 전압 제어 발진기의 변조 커패시터
뱅크를 사용하여 보정된다. 주파수 오프셋을 감지하고 보상하기 위한 목적으로
추가적인 회로를 사용하지 않아 면적이 증가하지 않고 소모 전력은 부정 피드백을
위해 동작하였던 분주기, 위상-주파수 검출기, 차지펌프의 소모 전력만큼 줄어들게
된다. 제안하는 구동증폭기는 왜곡 없는 스펙트럼 방사 마스크 성능을 위해 동작이
시작된 뒤 최소 파워부터 최대 파워까지 출력 파워가 부드럽게 증가해 급격한 출력
파워 변화가 발생하지 않도록 구현되었다.
제안된 열린 루프 변조를 수행하는 아날로그 위상동기루프는 닫힌 루프 변조일
때보다 600 µA 더 적은 전류가 흐르며 0.8 V의 공급전압에서 1.1 mW의 전력을
소모하고 구동증폭기는 4.9 mw의 전력을 소모한다. 칩의 면적은 1.17 mm²이며
55 nm CMOS 공정을 사용하였다. 측정 결과 열린 루프 변조에서 발생하는
오프셋이 보정되는 것을 확인 하였다.

목차 (Table of Contents)

• Ⅰ. Introduction 1
• Ⅱ. Bluetooth Low Energy Advertising System 4
• 2.1. Operation Scenario of BLE Advertising System 4
• 2.2. Requirements of BLE Advertising System 6
• 2.3. Design Specification of BLE Advertising Transceiver 7
• 2.4. Conventional Transceiver Modulation Architecture 10
• Ⅲ. Proposed System Architecture 16
• Ⅳ. Building Blocks 19
• 4.1. Analog PLL with Open-Loop Modulation 19
• 4.2. DA with Smooth Ramping 36
• Ⅴ. Experimental Results 45
• Ⅵ. Conclusion 56
• References 57
• Korean Abstract 61

참고문헌 (Reference)

1. ClassC PAVCO cell for FSK and GFSK transmitters,, C. Li et al., vol. 51, no. 7, pp. 1537–1546, , 2016

2. Selfcalibrated digital twopoint modulator for BLE RF transmitter, D. G. Kim et al., IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 69, no. 12, pp. 4739–4743, , 2022

3. A subnW 2.4 GHz transmitter for low datarate sensing applications,, P. P. Mercier et al., vol. 49, no. 7, pp. 1463– 1474, , 2014

4. A spurfree MASH digital deltasigma modulator with higher order shaped dither, B. Fitzgibbon et al., IEEE International Symposium on Radio Frequency Integration Technology (RFIT), pp. 723–726, , 2009

5. selfcalibrated twopoint deltasigma modulation technique for RF transmitters,, S. Lee et al., IEEE Trans. Microw. Theory Techn., vol. 58, no. 7, pp. 1748–1757, , 2010

6. A 8mWRX/113mWTX, subGHz SoC with timedithered PA ramping for LPWAN application, H. Gul et al., ESSCIRC, pp. 376–379, , 2017

7. A 2.4GHz fractionalN PLL with a PFD/CP linearization and an improved CP circuit, C. –L. Ti et al., IEEE Trans. Microw. Theory Techn., vol. 58, no. 7, pp. 1748–1757, , 2010

8. A +10 dBm 2.4 GHz transmitter with sub400 pW leakage and 43.7% system efficiency, A. Paidimarri, et al., in IEEE Int. SolidState Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 246247, , 2015

9. Time variant digital sigmadelta modulator for fractionalN frequency synthesizers, F. Maloberti, et al., European Conference on Circuit Theory and Design, pp. 111–114, , 2009

10. A crystalless BLE Transmitter with clock recovery from GFSKmodulated BLE packets,, X. Chen et al., vol. 56, no. 7, pp. 1963–1974, , 2021

11. A multimode WPAN (Bluetooth, BLE, IEEE 802.15.4) SoC for lowpower and IoT applications, A. Zolfaghari et al., pp. 74–75, , 2017

12. A 1.9mW 750kb/s 2.4GHz FOOK transmitter with symmetric FM template and highpoint modulation PLL,, Y. Zhang et al., vol. 52, no. 10, pp. 2627–2635, , 2017

13. A 5GHz subsampling PLLbased spreadspectrum clock generator by calibrating the frequency deviation, S. G. Bae et al., IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 64, no. 10, pp. 1132–1136, , 2017

14. A fully integrated Bluetooth lowenergy transmitter in 28 nm CMOS with 36% system efficiency at 3 dBm,, M. Babaie et al., vol. 51, no. 7, pp. 1547–1565, , 2016

15. A hybrid loop twopoint modulator without DCO nonlinearity calibration by utilizing 1 bit highpass modulation,, N. Wu et al., vol. 49, no. 10, pp. 2172–2186, , 2014

16. A low phase noise open loop fractionalN frequency synthesizer with injection locking digital phase modulator,, C. Yan et al., IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 3, pp. 455–459, , 2020

17. A DPLLcentric Bluetooth lowenergy transceiver with a 2.3mW interferencetolerant hybridloop receiver in 65nm CMOS,, H. Liu et al., vol. 53, no. 12, pp. 3672–3687, , 2018

18. A 1.9 nJ/b 2.4 GHz multistandard (Bluetooth low energy/Zigbee/IEEE802.15.6) transceiver for personal/bodyarea networks, Y. H. Liu et al., in IEEE Int. SolidState Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 446447, , 2013

19. A 6.3mW BLE transceiver embedded RX imagerejection filter and TX harmonicsuppression filter reusing onchip matching network, T. Sano et al., IEEE ISSCC, pp. 240–241, , 2015

20. A 0.3to1GHz IoT transmitter employing pseudorandomized phase switching modulator and singlesupply classG harmonic rejection PA,, K.S. Choi et al., vol. 57, no. 3, pp. 892–905, , 2015

21. A 28μW IoT tag that can communicate with commodity WiFi transceivers via a singlesideband QPSK backscatter communication technique, P.H. P. Wang et al., IEEE ISSCC, pp. 312–313, , 2020

22. A passive bidirectional BLE tag demonstrating batteryfree communication in tablet/smartphonetotag, tagtotablet/ smartphone, and tagtotag modes, Z. Chang et al., IEEE ISSCC, pp. 468–469, , 2023

23. An 860 μW 2.1to2.7 GHz alldigital PLLbased frequency modulator wirh a DTCassisted snapshot TDC for WPAN (Bluetooth smart and Zigbee) applications, V. K. Chillara, et al., in IEEE Int. SolidState Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 172173., , 2014

24. A 3.7 mWRx 4.4 mWTX fully integrated Bluetooth lowenergy/IEEE802.15.4/Proprietary SoC with an ADPLLbased fast frequency offset compensation in 40 nm CMOS, Y. H. Liu et al., in IEEE Int. SolidState Circuits Conf. (ISSCC) Dig. Tech. Papers, , 2015